Abstract: A vertically diffused FET (10) is fabricated on a semiconductor die (11) that includes an N+ substrate (12) and an N− epitaxial layer (14). The FET (10) has a source region (36) and a channel region (38) near a front surface (15) of the epitaxial layer (14), and a drain region in the substrate (12). A trench (22) extends through the epitaxial layer (14) to the substrate (12). A conductive layer (24) fills the trench (22), thereby forming a conductive plug (25) electrically coupled to the substrate (12). The conductive plug (25) forms a top side drain electrode of the FET (10).

Abstract: A single level gate NVM device (20) includes a floating gate FET (11) and a capacitor (12) fabricated in two P-wells (27, 28) formed in an N-epitaxial layer (22) on a P-substrate (21). P+ sinkers (29, 31) and N-type buried layers (25, 26) provide isolation between the two P-wells (27, 28). The NVM device (20) is programmed or erased by biasing the FET (11) and the capacitor (12) to move charge carriers onto or away from a conductive layer (36) which serves as a floating gate (14) of the FET (11). Data is read from the NVM device (20) by sensing a current flowing in the FET (11) while applying a reading voltage to the capacitor (12).

Abstract: A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

Abstract: A metallization process for semiconductor devices wherein the metal deposition steps are performed at higher wafer temperatures than subsequent processing steps. The correlation between wafer temperature and maximum grain width is prevalent in many metals used for semiconductor device metallization such as aluminum. Therefore, by measuring and controlling the maximum grain width of the deposited metal during metal deposition steps, it is possible to control and adjust the wafer temperature.