Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

Abstract: A sensing device, a method for fabrication thereof, and a method for operating the same are disclosed. The sensing device includes a flexible substrate, a first metallization layer, a piezoelectric thin film layer, a second metallization layer, and an insulating layer. The first metallization layer forms at least a source region and at least a drain region. The piezoelectric thin film layer provides a channel region permitting passage of charge carriers between the source region and the drain region. The second metallization layer forms at least a gate electrode and regulates flow of charge carriers through the piezoelectric thin film layer. When subjected to an external force, the flow of charge carriers is modulated in response to a strain in the piezoelectric thin film layer. The force is measured as a correlation between the applied force and the modulation of the flow of charge carriers.

Abstract: An apparatus for energy conversion, comprising a piezoelectric component comprising a first part configured to convert vibrational energy into electrical energy; and an output for sending a first portion of the generated electrical energy to an electronic device, and a feedback loop for feeding a second portion of the generated electrical energy to a second part of the piezoelectric component, wherein the second part of the piezoelectric component is coupled to the first part of the piezoelectric component and is configured to convert electrical energy into vibrational energy thereby causing the first part of the piezoelectric component to vibrate.

Abstract: A sensing device, a method for fabrication thereof, and a method for operating the same are disclosed. The sensing device includes a flexible substrate, a first metallisation layer, a piezoelectric thin film layer, a second metallisation layer, and an insulating layer. The first metallization layer forms at least a source region and at least a drain region. The piezoelectric thin film layer provides a channel region permitting passage of charge carriers between the source region and the drain region. The second metallization layer forms at least a gate electrode and regulates flow of charge carriers through the piezoelectric thin film layer. When subjected to an external force, the flow of charge carriers is modulated in response to a strain in the piezoelectric thin film layer. The force is measured as a correlation between the applied force and the modulation of the flow of charge carriers.

Abstract: An apparatus for energy conversion, comprising a piezoelectric component comprising a first part configured to convert vibrational energy into electrical energy; and an output for sending a first portion of the generated electrical energy to an electronic device, and a feedback loop for feeding a second portion of the generated electrical energy to a second part of the piezoelectric component, wherein the second part of the piezoelectric component is coupled to the first part of the piezoelectric component and is configured to convert electrical energy into vibrational energy thereby causing the first part of the piezoelectric component to vibrate.

Abstract: A low contact resistance and low junction leakage metal interconnect contact structure for use with ICs. The contact structure includes an interconnect dielectric material layer on the surface of an IC semiconductor substrate. The interconnect dielectric material layer has a contact opening which extends to a predetermined region of the semiconductor substrate (e.g. a source region, drain region, or polysilicon gate layer). The contact structure also includes a cobalt (or nickel) silicide interface layer on the surface of the predetermined region that is aligned with the bottom of the contact opening, a cobalt (or nickel) adhesion layer on the sidewall surface of the contact opening, a refractory metal-based barrier layer on the metal adhesion layer and the metal silicide interface layer, and a conductive plug. Manufacturing process steps for such a contact structure include first providing a semiconductor substrate with at least one predetermined region (e.g.

Abstract: Integrated circuit memory elements are fabricated by disposing a first layer of electrically conductive material on the surface of an electrically insulating substrate. The first layer of electrically conductive material is formed into a first predetermined pattern. A second layer of electrically insulating material is disposed on the surface of the electrically insulating substrate and the patterned first layer of electrically conductive material. A first layer of magnetizable material is disposed on the second insulating layer and is formed into a predetermined pattern having a predetermined positional relationship with respect to the underlying patterned first layer of electrically conductive material. A third layer of electrically insulating material is disposed over the second layer of insulating material and the patterned first layer of magnetizable material.

Abstract: An integrated circuit electronic grid device includes first and second metal layers wherein the metal layers are vertically disposed within a substitute. A layer of a dielectric medium is disposed between the metal layers and a third metal layer is spaced apart from the second metal layer and insulated from the second metal layer by another layer of a dielectric medium. The first and second metal layers are biased with respect to each other to cause a flow electrons from the first metal layer toward the second metal layer. The second metal layer is provided with a large plurality of holes adapted for permitting the flow of electrons to substantially pass therethrough and to travel toward the third metal layer. A fourth metal layer is spaced apart from the third metal layer to collect the electrons wherein the third metal layer is also provided with a large plurality of holes to permit the electrons to flow therethrough and continue toward the fourth metal layer.

Abstract: A low temperature method of forming silica-containing ceramic coatings on substrates in which a coating containing hydrogen silsesquioxane resin is applied on a substrate and exposed to an electron beam for a time sufficient to convert the hydrogen silsesquioxane resin to the silica-containing ceramic coating. This method is especially valuable for forming protective and dielectric coatings on electronic devices.

Abstract: An integrated circuit electronic grid device includes first and second metal layers wherein the metal layers are vertically disposed within a substitute. A layer of a dielectric medium is disposed between the metal layers and a third metal layer is spaced apart from the second metal layer and insulated from the second metal layer by another layer of a dielectric medium. The first and second metal layers are biased with respect to each other to cause a flow electrons from the first metal layer toward the second metal layer. The second metal layer is provided with a large plurality of holes adapted for permitting the flow of electrons to substantially pass therethrough and to travel toward the third metal layer. A fourth metal layer is spaced apart from the third metal layer to collect the electrons wherein the third metal layer is also provided with a large plurality of holes to permit the electrons to flow therethrough and continue toward the fourth metal layer.

Abstract: An integrated circuit microwave interconnect is formed upon a surface by disposing a dielectric layer over the surface and patterning the dielectric layer to form a dielectric region. The dielectric region is then surrounded by a surrounding metal layer. In one embodiment the surface may be a non-metal upon which a metal layer is disposed prior to disposing the dielectric layer. In this embodiment an additional metal layer is disposed adjoining the first metal surface on both sides of the dielectric region after patterning the layer to form the dielectric region. Thus, the two metal layers thereby form the surrounding metal layer around the dielectric region. The microwave interconnect may be formed upon the surface of the substrate, above the surface of the substrate in a floating configuration, or in a trench within the substrate.

Abstract: A process for fabricating discrete electrical microcomponents, such as microtransformers, microautotransformers and microinductors, on a semiconductor substrate in which two patterned layers of electrically conductive material are electrically connected through vias in two interposed layers of electrically insulating material to form electrically conductive coils around a magnetic core formed by a patterned layer of magnetic material interposed between the two insulating layers. Laminated magnetic cores may be formed by patterning multiple layers of magnetic material. The microcomponents can also be formed without magnetic cores and can be formed on insulating substrates.