Abstract: The present disclosure describes an artificial neural network circuit including: at least one crossbar circuit to transmit a signal between layered neurons of an artificial neural network, the crossbar circuit including multiple input bars, multiple output bars arranged intersecting the input bars, and multiple memristors that are disposed at respective intersections of the input bars and the output bars to give a weight to the signal to be transmitted; a processing circuit to calculate a sum of signals flowing into each of the output bars while a weight to a corresponding signal is given by each of the memristors; a temperature sensor to detect environmental temperature; and an update portion that updates a trained value used in the crossbar circuit and/or the processing circuit.

Abstract: A convolutional neural network includes: convolution layers and a merging layer. At least one convolution layer includes a crossbar circuit having input bars, output bars and weight assignment elements that assign weights to input signals. The crossbar circuit performs a convolution operation in an analog region with respect to input data including the input signal by adding the input signals at each output bar. The input data includes feature maps. The crossbar circuit includes a first crossbar circuit for performing the convolution operation with respect to a part of the feature maps and a second crossbar circuit for performing the convolution operation with respect to another part of feature maps. The merging layer merges convolution operation results of the first and second crossbar circuits.

Abstract: An artificial neural network circuit includes a crossbar circuit, and a processing circuit. The crossbar circuit transmits a signal between layered neurons of an artificial neural network. The crossbar circuit includes input bars, output bars arranged intersecting the input bars, and memristors. The processing circuit calculates a sum of signals flowing into each of the output bars. The processing circuit calculates, as the sum of the signals, a sum of signals flowing into a plurality of separate output bars and conductance values of the corresponding memristors are set so as to cooperate to give a desired weight to the signal to be transmitted.

Abstract: A method for training an artificial neural network circuit is provided. The artificial neural network circuit includes a crossbar circuit that has a plurality of input bars, a plurality of output bars crossing the plurality of input bars, and memristors each of which includes a variable conductance element provided at corresponding one of intersections of the input bars and the output bars.

Abstract: A image recognition system includes a first convolution layer, a pooling layer, a second convolution layer, a crossbar circuit having a plurality of input lines, at least one output line intersecting with the input lines, and a plurality of weight elements that are provided at intersection points between the input lines and the output line, weights each input value input to the input lines to output to the output line, and a control portion that selects from convolution operation results of the first convolution layer, an input value needed to acquire each pooling operation result needed to perform second filter convolution operation at each shift position in the second convolution layer, and inputs the input value selected to the input lines.

Abstract: A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

Abstract: A neural network circuit includes: a storage portion that includes memristors; D/A converters; drive amplifiers; I/V conversion amplifiers; A/D converters; and offset correctors. The offset corrector includes a first latch circuit, a second latch circuit, a subtractor that subtracts latch data, and a controller. In performing a bias setting operation, the controller controls a bias application amplifier to output the bias voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output a reference voltage, and also cause the first latch circuit to latch the output data. In performing a normal operation, the controller controls the bias application amplifier to output the reference voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output the signal voltage, and also cause the second latch circuit to latch the output data.

Abstract: A neural network circuit is provided. The neural network circuit includes a memory device including memristors connected in a matrix, a controller arranged to control a voltage application device to perform writing, deleting and reading data in the memory device, multiple current-to-voltage (I-V) conversion amplifier circuits arranged to convert currents flowing through the memory elements into voltages and outputting the voltages, and multiple current adjusters respectively corresponding to the I-V conversion amplification circuits, each current adjuster being arranged to adjust a total current value input to a corresponding I-/V conversion amplification circuit to zero.

Abstract: A neural network circuit includes: a storage part that includes memristors in a lattice shape; a voltage application circuit that applies a bias voltage to the storage part; a controller that controls the voltage application circuit to perform to a selection element, writing, erasing, or reading; and multiple conversion amplification circuits that convert a current flowing into a voltage, and output the voltage.

Abstract: A image recognition system includes a first convolution layer, a pooling layer, a second convolution layer, a crossbar circuit having a plurality of input lines, at least one output line intersecting with the input lines, and a plurality of weight elements that are provided at intersection points between the input lines and the output line, weights each input value input to the input lines to output to the output line, and a control portion that selects from convolution operation results of the first convolution layer, an input value needed to acquire each pooling operation result needed to perform second filter convolution operation at each shift position in the second convolution layer, and inputs the input value selected to the input lines.

Abstract: The present disclosure describes an artificial neural network circuit including: at least one crossbar circuit to transmit a signal between layered neurons of an artificial neural network, the crossbar circuit including multiple input bars, multiple output bars arranged intersecting the input bars, and multiple memristors that are disposed at respective intersections of the input bars and the output bars to give a weight to the signal to be transmitted; a processing circuit to calculate a sum of signals flowing into each of the output bars while a weight to a corresponding signal is given by each of the memristors; a temperature sensor to detect environmental temperature; and an update portion that updates a trained value used in the crossbar circuit and/or the processing circuit.

Abstract: A method for training an artificial neural network circuit is provided. The artificial neural network circuit includes a crossbar circuit that has a plurality of input bars, a plurality of output bars crossing the plurality of input bars, and memristors each of which includes a variable conductance element provided at corresponding one of intersections of the input bars and the output bars.

Abstract: A method for adjusting output level of a neuron in a multilayer neural network is provided. The multilayer neural network includes a memristor and an analog processing circuit, causing transmission of the signals between the neurons and the signal processing in the neurons to be performed in an analog region. The method includes an adjustment step that adjusts an output level of the neurons of each of the layers, causing the output value to become lower than a write threshold voltage of the memristor and to fall within a maximum output range set for the analog processing circuit executing the generation of the output value in accordance with the activation function when each of the output values of the neurons of each of the layers becomes highest.

Abstract: An artificial neural network circuit includes a crossbar circuit, and a processing circuit. The crossbar circuit transmits a signal between layered neurons of an artificial neural network. The crossbar circuit includes input bars, output bars arranged intersecting the input bars, and memristors. The processing circuit calculates a sum of signals flowing into each of the output bars. The processing circuit calculates, as the sum of the signals, a sum of signals flowing into a plurality of separate output bars and conductance values of the corresponding memristors are set so as to cooperate to give a desired weight to the signal to be transmitted.

Abstract: A convolutional neural network includes: convolution layers and a merging layer. At least one convolution layer includes a crossbar circuit having input bars, output bars and weight assignment elements that assign weights to input signals. The crossbar circuit performs a convolution operation in an analog region with respect to input data including the input signal by adding the input signals at each output bar. The input data includes feature maps. The crossbar circuit includes a first crossbar circuit for performing the convolution operation with respect to a part of the feature maps and a second crossbar circuit for performing the convolution operation with respect to another part of feature maps. The merging layer merges convolution operation results of the first and second crossbar circuits.

Abstract: A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

Abstract: A neural network circuit is provided. The neural network circuit includes a memory device including memristors connected in a matrix, a controller arranged to control a voltage application device to perform writing, deleting and reading data in the memory device, multiple current-to-voltage (I-V) conversion amplifier circuits arranged to convert currents flowing through the memory elements into voltages and outputting the voltages, and multiple current adjusters respectively corresponding to the I-V conversion amplification circuits, each current adjuster being arranged to adjust a total current value input to a corresponding I-/V conversion amplification circuit to zero.

Abstract: A neural network circuit includes: a storage portion that includes memristors; D/A converters; drive amplifiers; I/V conversion amplifiers; A/D converters; and offset correctors. The offset corrector includes a first latch circuit, a second latch circuit, a subtractor that subtracts latch data, and a controller. In performing a bias setting operation, the controller controls a bias application amplifier to output the bias voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output a reference voltage, and also cause the first latch circuit to latch the output data. In performing a normal operation, the controller controls the bias application amplifier to output the reference voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output the signal voltage, and also cause the second latch circuit to latch the output data.

Abstract: A neural network is implemented as a memristive neuromorphic circuit that includes a neuron circuit and a memristive device connected to the neuron circuit. An input voltage is sensed at a first terminal of a memristive device during a feedforward operation of the neural network. An error voltage is sensed at a second terminal of the memristive device during an error backpropagation operation of the neural network. In accordance with a training rule, a desired conductance change for the memristive device is computed based on the sensed input voltage and the sensed error voltage. Then a training voltage is applied to the memristive device. Here, the training voltage is proportional to a logarithmic value of the desired conductance change.

Abstract: A neural network circuit includes: a storage part that includes memristors in a lattice shape; a voltage application circuit that applies a bias voltage to the storage part; a controller that controls the voltage application circuit to perform to a selection element, writing, erasing, or reading; and multiple conversion amplification circuits that convert a current flowing into a voltage, and output the voltage.