Patents by Inventor Irina V. Vasilyeva
Irina V. Vasilyeva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240164114Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.Type: ApplicationFiled: November 29, 2023Publication date: May 16, 2024Applicant: Micron Technology, Inc.Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
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Patent number: 11923272Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.Type: GrantFiled: April 15, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
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Patent number: 11871582Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.Type: GrantFiled: January 31, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
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Publication number: 20220238417Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.Type: ApplicationFiled: April 15, 2022Publication date: July 28, 2022Applicant: Micron Technology, Inc.Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
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Publication number: 20220157837Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Micron Technology, Inc.Inventors: Hung-Wei Liu, Vassil N, Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffrey B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
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Patent number: 11335626Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.Type: GrantFiled: September 15, 2020Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
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Publication number: 20220093617Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.Type: ApplicationFiled: September 21, 2020Publication date: March 24, 2022Applicant: Micron Technology, Inc.Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
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Publication number: 20220084906Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Applicant: Micron Technology, Inc.Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
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Patent number: 11264395Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.Type: GrantFiled: September 21, 2020Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
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Patent number: 10923478Abstract: Methods, apparatuses, and systems related to reduction of roughness on a sidewall of an opening are described. An example method includes forming a liner material on a first sidewall of an opening in a first silicate material and on a second sidewall of the opening in an overlying second silicate material, where the liner material is formed to a thickness that covers a roughness on the first sidewall extending into the opening. The example method further includes removing the liner material from the first sidewall of the opening and the second sidewall of the opening with a non-selective etch chemistry to reduce the roughness on the first sidewall.Type: GrantFiled: January 28, 2019Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Christopher J. Gambee, Devesh Dadhich Shreeram, Irina V. Vasilyeva
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Publication number: 20200243535Abstract: Methods, apparatuses, and systems related to reduction of roughness on a sidewall of an opening are described. An example method includes forming a liner material on a first sidewall of an opening in a first silicate material and on a second sidewall of the opening in an overlying second silicate material, where the liner material is formed to a thickness that covers a roughness on the first sidewall extending into the opening. The example method further includes removing the liner material from the first sidewall of the opening and the second sidewall of the opening with a non-selective etch chemistry to reduce the roughness on the first sidewall.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Inventors: Christopher J. Gambee, Devesh Dadhich Shreeram, Irina V. Vasilyeva
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Patent number: 10163655Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.Type: GrantFiled: November 20, 2015Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventors: Jin Lu, Rita J. Klein, Diem Thy N. Tran, Irina V. Vasilyeva, Zhiqiang Xie
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Patent number: 9761797Abstract: Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.Type: GrantFiled: June 27, 2016Date of Patent: September 12, 2017Assignee: Micron Technology, Inc.Inventors: Hyun Sik Kim, Irina V. Vasilyeva, Kyle B. Campbell, Kyuchul Chong
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Publication number: 20170148674Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.Type: ApplicationFiled: November 20, 2015Publication date: May 25, 2017Inventors: JIN LU, RITA J. KLEIN, DIEM THY N. TRAN, IRINA V. VASILYEVA, ZHIQIANG XIE
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Publication number: 20160308126Abstract: Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Hyun Sik Kim, Irina V. Vasilyeva, Kyle B. Campbell, Kyuchul Chong
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Patent number: 9401474Abstract: Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.Type: GrantFiled: July 1, 2014Date of Patent: July 26, 2016Assignee: Micron Technology, Inc.Inventors: Hyun Sik Kim, Irina V. Vasilyeva, Kyle B. Campbell, Kyuchul Chong
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Publication number: 20160005966Abstract: Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.Type: ApplicationFiled: July 1, 2014Publication date: January 7, 2016Inventors: Hyun Sik Kim, Irina V. Vasilyeva, Kyle B. Campbell, Kyuchul Chong