Abstract: A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon.

Abstract: A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon.

Abstract: A method for forming diffusions having narrow, for example, submicrometer dimensions in a silicon body which involves forming insulator regions on a silicon body, which insulator regions have substantially horizontal surfaces and substantially vertical surfaces. A layer having a desired dopant concentration is formed thereon, both on the substantially horizontal surfaces and the substantially vertical surfaces. Reactive ion etching of the layer acts to substantially remove only the horizontal layer and provides a narrow dimensioned layer having a desired dopant concentration in the substantially vertical surfaces. Heating of the body at a suitable temperature is accomplished so as to produce the movement of the dopant into the silicon body by diffusion to form diffusions having narrow, such as submicrometer dimensions, therein.

Abstract: A method for forming a narrow, such as a submicrometer, dimensioned mask opening on a silicon body involving forming a first insulator region having substantially a horizontal surface and a substantially vertical surface. A second insulator is applied on both the horizontal surface and substantially vertical surfaces. The second insulator is composed of a material different from that of the first insulator layer. Reactive ion etching of the second layer removes the horizontal layer and provides a narrow dimensioned second insulator region on the silicon body. The surface of the silicon body is then thermally oxidized. The narrow dimensioned second insulator region is removed to form a narrow dimensioned mask opening.

Abstract: An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.

Abstract: A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate region has a threshold voltage determined by an impurity imparted thereto by either diffusion or ion implantation. The third or storage region has a lower threshold voltage than the gate region. A single unitary metal electrode extends in superimposed relation to the second and third regions. Upon the application of potentials to the first region and the electrode, charge carriers may be stored in or removed from the third region so as to write a "1" or a "0" in the cell.

Abstract: A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused therein and serves alternately as a source and a drain for charge carriers. The second or gate region has a predetermined threshold voltage and the third or storage region has a lower threshold voltage. A single unitary metal electrode extends in superimposed relation to the second and third regions. Upon the application of potentials to the first region and the electrode, charge carriers may be stored in or removed from the third region so as to write a "1" or a "0" in the cell.

Abstract: An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.