Abstract: An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.

Abstract: A voltage regulator system of an information handling system includes a Smart Power Stage (SPS) and a voltage regulator controller. The SPS includes a high-side transistor and a low-side transistor. The voltage regulator controller detects a normal power down of the information handling system and sets bleed state for the SPS to a first state. Based on the bleed state being set to the first state, the voltage regulator controller provides a first control voltage to the low-side transistor and a second control voltage to the high-side transistor. The first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region. In response to a predetermined amount of time expiring, the voltage regulator controller enters the SPS in an idle mode.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: An information handling system includes a compute express link (CXL) device coupled to a processor by a PCIe/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a CXL link signaling rate, trains the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, and operates the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link.

Abstract: An information handling system includes a processor and a memory module. The memory module operates with a base set of functions and is configurable to operate with an expanded set of functions. The memory module includes a data storage location to store expansion capability certificates that specify subsets of the expanded set of functions to enable. The processor creates an expansion capability certificate that includes a first unique identifier of the information handling system, a second unique identifier of the memory module, and a subset of the expanded set of functions, and provides the expansion capability certificate to the memory module. The memory module receives the first expansion capability certificate, stores the expansion capability certificate to the data storage location, and enables the subset of the expanded set of functions in response to storing the expansion capability certificate.

Abstract: A memory module includes first and second data storage locations. The first data storage location stores an expansion license. The memory module operates with a base set of functions, and is configurable to operate with an expanded set of functions based on the expansion license. The second data storage location stores an expansion capability certificate that is signed by an information handling system and includes a subset of the expanded set of functions that are enabled by the expansion capability certificate. The memory module determines that the memory module is installed into the information handling system based on the expansion capability certificate, and enables the subset of the expanded set of functions in response to determining that the memory module is installed into the information handling system.

Abstract: An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.

Abstract: An information handling system includes a printed circuit board (PCB) and an integrated circuit device. The integrated circuit device includes a substrate and a die that is bonded via a first surface of the die to a first surface of the substrate. The substrate includes a ball grid array (BGA) on the first surface of the substrate. The integrated circuit device is bonded to a first surface of the PCB via the BGA. The die is collocated with the cutout area.

Abstract: A memory module includes first and second data storage locations. The memory module operates with a full set of functions. When the first data storage location stores an expansion license, the memory module is configurable to operate with a subset of the full set of functions disabled. The second data storage location stores an expansion capability certificate, that is signed by an information handling system and includes a first subset of the full set of functions that are disabled by the expansion capability certificate. The memory module determines that the memory module is installed into the information handling system based on the expansion capability certificate, and disables the first subset of the full set of functions in response to determining that the memory module is installed into the information handling system.

Abstract: An information handling system includes processing nodes, a compute express link (CXL) switch, and CXL devices. A workload orchestrator receives a workload to be instantiated on a particular one of the processing nodes, determines a set of resources associated with the workload, selects a particular one of the CXL devices to be used based upon the set or resources, and launches the workload on the processing node.

Abstract: An information handling system includes a compute express link (CXL) device coupled to a processor by a PCIe/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a CXL link signaling rate, trains the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, and operates the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link.

Abstract: An information handling system includes a processor, first and second plug-in connector interfaces coupled to the processor, and first and second accelerator modules installed into respective first and second plug-in connector interfaces. The processor instantiates machine learning code. The information handling system instantiates a workload on the processor. The machine learning code determines a processing need of the workload, determines a first processing capability of the first accelerator module and a second processing capability of the second accelerator module, and allocates a processing resource of the first accelerator module to the workload based upon an evaluation of the processing need, the first processing capability, and the second processing capability.

Abstract: An interface apparatus for installing memory modules to an information handling system includes a riser card and an adapter. The riser card includes a first card-edge connector on a first edge of the riser card, and a second card-edge connector on a second edge of the riser card. The first card-edge connector is associated with a first interface and the second card-edge connector is associated with a second interface. The adapter includes a first socket on a first side of the adapter, and a second socket on a second side of the adapter opposite to the first side. The first socket and the second socket are associated with the second interface. The first socket is configured to receive the second card-edge connector of the riser card. The second socket is configured to receive a memory module.

Abstract: An information handling system includes an enclosure configured to include a duct to channel air flow in the enclosure over a first component of the information handling system. A duct sensor determines if the duct is included in the enclosure. The system receives an indication from the duct sensor that the duct is not included in the information handling system, determines that the first component is in a hot spot in the enclosure based upon the indication, and redirects a workload instantiated on the first component to a second component of the information handling system.

Abstract: An interface apparatus for installing an add-in module to an information handling system includes the add-in module and an add-in module socket. The add-in module includes a card-edge connector on a first edge of the add-in module, and an electrical contact finger on a second edge of the add-in module. The add-in module socket is affixed to the information handling system and receives the add-in module. The add-in module socket includes a card-edge connector interface for receiving the card edge connector, and a slot channel for receiving the second edge of the add-in module. The slot channel includes an electrical contact pad configured such that, when the add-in module is installed into the add-in module socket, a current is provided between the add-in module socket and the add-in module through the electrical contact pad and the electrical contact finger.

Abstract: An interface apparatus for installing an add-in module to an information handling system includes the add-in module and an add-in module socket. The add-in module includes a card-edge connector on a first edge of the add-in module, and an electrical contact finger on a second edge of the add-in module. The add-in module socket is affixed to the information handling system and receives the add-in module. The add-in module socket includes a card-edge connector interface for receiving the card edge connector, and a slot channel for receiving the second edge of the add-in module. The slot channel includes an electrical contact pad configured such that, when the add-in module is installed into the add-in module socket, a current is provided between the add-in module socket and the add-in module through the electrical contact pad and the electrical contact finger.