Patents by Inventor Isam Akkawi
Isam Akkawi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11868262Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.Type: GrantFiled: February 9, 2023Date of Patent: January 9, 2024Assignee: Marvell Asia Pte, Ltd.Inventors: Richard E. Kessler, David Asher, Shubhendu S Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
-
Publication number: 20230229595Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Inventors: Craig BARNER, David ASHER, Richard KESSLER, Bradley DOBBIE, Daniel DEVER, Thomas F. HUMMEL, Isam AKKAWI
-
Publication number: 20230205649Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Inventors: Andreas Nowatzyk, Pratap Subrahmanyam, Isam Akkawi
-
Publication number: 20230185720Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.Type: ApplicationFiled: February 9, 2023Publication date: June 15, 2023Inventors: Richard E. Kessler, David Asher, Shubhendu S. Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
-
Patent number: 11620223Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: GrantFiled: August 12, 2021Date of Patent: April 4, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
-
Patent number: 11620192Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).Type: GrantFiled: July 10, 2020Date of Patent: April 4, 2023Assignee: VMware, Inc.Inventors: Andreas Nowatzyk, Pratap Subrahmanyam, Isam Akkawi
-
Patent number: 11615027Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.Type: GrantFiled: November 18, 2021Date of Patent: March 28, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Richard E. Kessler, David Asher, Shubhendu S. Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
-
Publication number: 20220114101Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.Type: ApplicationFiled: November 18, 2021Publication date: April 14, 2022Inventors: Richard E. KESSLER, David ASHER, Shubhendu S. MUKHERJEE, Wilson P. SNYDER, II, David CARLSON, Jason ZEBCHUK, Isam AKKAWI
-
Publication number: 20220012139Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Inventors: Andreas Nowatzyk, Pratap Subrahmanyam, Isam Akkawi
-
Publication number: 20210374057Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Inventors: Craig BARNER, David ASHER, Richard KESSLER, Bradley DOBBIE, Daniel DEVER, Thomas F. HUMMEL, Isam AKKAWI
-
Patent number: 11188466Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.Type: GrantFiled: February 11, 2020Date of Patent: November 30, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Richard E. Kessler, David Asher, Shubhendu S. Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
-
Patent number: 11119929Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: GrantFiled: January 31, 2019Date of Patent: September 14, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
-
Publication number: 20200252434Abstract: A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.Type: ApplicationFiled: April 21, 2020Publication date: August 6, 2020Inventors: Isam Akkawi, Darren Braun, Wilson Parkhurst Snyder, II, Bryan Chin
-
Publication number: 20200250088Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: ApplicationFiled: January 31, 2019Publication date: August 6, 2020Inventors: Craig Barner, David Asher, Richard Kessler, Brad Dobbie, Daniel Dever, Tom Hummel, Isam Akkawi
-
Publication number: 20200183844Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.Type: ApplicationFiled: February 11, 2020Publication date: June 11, 2020Inventors: Richard E. KESSLER, David ASHER, Shubhendu S. MUKHERJEE, Wilson P. SNYDER, II, David CARLSON, Jason ZEBCHUK, Isam AKKAWI
-
Patent number: 10666682Abstract: A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can be booted securely. The network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. The network chip is configured to allow the BMC to access a plurality of registers of the network chip via a Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.Type: GrantFiled: September 30, 2015Date of Patent: May 26, 2020Assignee: Marvell Asia Pte, Ltd.Inventors: Isam Akkawi, Darren Braun, Wilson Parkhurst Snyder, II, Bryan Chin
-
Patent number: 10558573Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.Type: GrantFiled: September 11, 2018Date of Patent: February 11, 2020Assignee: Cavium, LLCInventors: Richard E. Kessler, David Asher, Shubhendu S. Mukherjee, Wilson P. Snyder, II, David Carlson, Jason Zebchuk, Isam Akkawi
-
Patent number: 10007614Abstract: System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.Type: GrantFiled: February 2, 2016Date of Patent: June 26, 2018Assignee: Cavium, Inc.Inventors: Xiaodong Wang, Srilatha Manne, Bryan Wai Chin, Isam Akkawi, David Asher
-
Patent number: 10002218Abstract: A system includes a formal verification engine running on a host and a protocol checking engine. The formal verification engine automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level. The formal verification engine is further configured to automatically generate a plurality of self-contained services from the plurality of extended state tables. A self-contained service of the plurality of self-contained services is randomly and atomically executable. The self-contained service of the plurality of self-contained services changes responsive to the IC design protocol changing. The protocol checking engine checks and validates completeness and correctness of the self-contained service of the reference specification.Type: GrantFiled: March 9, 2016Date of Patent: June 19, 2018Assignee: Cavium, Inc.Inventors: Shahid Ikram, Isam Akkawi, Richard Eugene Kessler, James Ellis, David Asher
-
Publication number: 20170220477Abstract: System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.Type: ApplicationFiled: February 2, 2016Publication date: August 3, 2017Inventors: Xiaodong Wang, Srilatha Manne, Bryan Wai Chin, Isam Akkawi, David Asher