Abstract: A semiconductor memory device is capable of performing a faster operation by reducing a load applied to a subword selection line or driving a subword driver provided for each memory mat. In a drive method of subword drivers that are actuated in response to subword selection signals supplied through subword selection lines, the subword selection lines are branched according to the number of memory mats. Each subword selection signal has a polarity to a branching position and an inverted polarity from each branching position to each subword driver. The inverted subword selection signal together with a main word signal are calculated to operation in each subword driver and output as a subword drive signal. The plurality of subword drivers share an inverter circuit for inverting the main word signals so as to permit a simplified circuit configuration.

Abstract: A semiconductor memory device is capable of performing a faster operation by reducing a load applied to a subword selection line or driving a subword driver provided for each memory mat. In a drive method of subword drivers that are actuated in response to subword selection signals supplied through subword selection lines, the subword selection lines are branched according to the number of memory mats. Each subword selection signal has a polarity to a branching position and an inverted polarity from each branching position to each subword driver. The inverted subword selection signal together with a main word signal are calculated to operation in each subword driver and output as a subword drive signal. The plurality of subword drivers share an inverter circuit for inverting the main word signals so as to permit a simplified circuit configuration.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: A low noise and lower power consumption receiver including a CRC error correction circuit which is constructed at low cost, prolongs a life of a battery and enhances a receiving sensitivity. The receiver comprises a data processing unit which continuously determines errors in received data encoded by a CRC code and corrects them by comparing with reference syndrome patterns, a microprocessor circuit including a data RAM connected with local data buses and local address buses and a serial data receiving apparatus including state control means, a synchronizing circuit, an ID comparing circuit and a circuit for gating system clock. The high performance and low power consumption receiver may be realized with less additional circuits, having more flexibility to the increase of services.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are occupied by capacitors formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: An IC for communication includes a single oscillating circuit, which is capable of flexibly dealing with the change of data rate or data processing load, and is produced at a low cost and consumes low electric power. In the IC for communication, a frequency multiplying circuit(61) is inserted between the output of an oscillating circuit(1) and a micro-controller circuit(69), or a frequency dividing circuit(2) is inserted between the oscillating circuit(1) and a data receiving circuit(3). A receiving address is stored in a dual port RAM(16). Further, by controlling a receiving frequency of synchronous codes, battery saving efficiency is increased.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.

Abstract: In a selected paging signal type receiving apparatus, a transmission code is received which is arranged by coupling a series of signal codes including a preamble, a sync code, and a message code. Even when signal reception is interrupted, this receiving apparatus can immediately respond to an interference condition and a completion of a signal transmission. In the case of the interference condition, the receiving apparatus can be immediately recovered to the signal reception operation after the interference condition disappears.

Abstract: In a diaphragm type gas meter, one crank plate pivotally mounting a pair of diaphragm movement transmission levers and the other crank plate pivotally mounting a pair of valve actuating levers overlap each other rockably around the central axis of a crank shaft. The relative angular position of the two plates is controlled e.g. by an eccentric cam. On a diaphragm control wall member for restricting the stroke end of the reciprocation of each measuring diaphragm of said gas meter are formed two inclined diaphragm control surfaces with different angles of inclination. Further, on a lower casing of the gas meter is integrally die-cast a partition wall with triangular section flush with the top surface of the lower casing and defining a discharge-side valve chamber and a discharge passage.