Patents by Inventor Isamu Kotaka

Isamu Kotaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11217705
    Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: January 4, 2022
    Assignee: NTT ELECTRONICS CORPORATION
    Inventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
  • Publication number: 20190312150
    Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).
    Type: Application
    Filed: June 6, 2019
    Publication date: October 10, 2019
    Inventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
  • Patent number: 10367100
    Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 30, 2019
    Assignee: NTT ELECTRONICS CORPORATION
    Inventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
  • Publication number: 20170323981
    Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).
    Type: Application
    Filed: August 13, 2015
    Publication date: November 9, 2017
    Inventors: Makoto SHIMIZU, Hiroki ITOH, Tadao ISHIBASHI, Isamu KOTAKA
  • Patent number: 4751170
    Abstract: A silylation method wherein a resist coating applied on a substrate is reacted with an organic silane compound under the irradiation of a deep ultraviolet ray to render regions of the resist coating durable to oxidative ion etching, whereby a fine pattern is formed. The resist coating includes a layer of an active polymer which is reactive with an organic silane compound under the irradiation of a deep ultraviolet ray to be combined with silyl groups, and a layer of an inert polymer which is not reactive with an organic silicone compound under the irradiation of a deep ultraviolet ray. A desired pattern is formed with the resist coating by ordinary lithographic technique, and then the active polymer layer of the pattern is allowed to contact with an organic silane compound while being irradiated with a deep ultraviolet ray to introduce silyl groups into the active polymer layer of the pattern so as to form masking regions durable to oxidative ion etching.
    Type: Grant
    Filed: July 23, 1986
    Date of Patent: June 14, 1988
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yoshiaki Mimura, Isamu Kotaka, Mineo Ueki