Abstract: A vehicle security system includes a reception device that is mounted on a vehicle, and a transmission device that remotely operates the vehicle. The transmission device includes an encryption section that encrypts identification information that identifies the transmission device with a first encryption key, and a transmission section that transmits to the reception device instruction information that includes the identification information encrypted and gives an operation instruction to the reception device.

Abstract: A communication system includes: a transmission device; and a reception device, wherein the transmission device includes an encryption section that encrypts a plaintext to be transmitted to the reception device with a first encryption key, and a transmission section that transmits the encrypted plaintext to the reception device; and the reception device includes a FeRAM that stores a second encryption key to pair with the first encryption key, wherein, upon reading out the second encryption key from the FeRAM, the second encryption key is erased from the FeRAM, a reception section that receives the encrypted plaintext from the transmission device, and a decoding section that decodes the received plaintext encrypted with the first encryption key with the second encryption key that is supposed to be stored in the FeRAM.

Abstract: A data processing device includes: an execution unit; and a memory unit, wherein the memory unit stores a plurality of pre-processing data on which a processing is to be rendered at a plurality of times prior to a specified time; (1) when a value of specified pre-processing data at the specified time is in a range between a maximum value and a minimum value among values of the plurality of pre-processing data, the execution unit renders the processing on the specified pre-processing data; and (2) when the value of the specified pre-processing data is greater than the maximum value or smaller than the minimum value, the execution unit renders the processing on an arbitrary value that is deemed substantively in the range between the maximum value and the minimum value, instead of the value of the specified pre-processing data.

Abstract: A semiconductor device includes: a rewritable ferroelectric memory including an encryption table containing one or more data codes paired with encryption codes that are the data codes encrypted, a first region for storing the encryption codes, a second region for storing the data codes, and a third region for storing one or more of the data codes, wherein, when the encryption code is stored in the first region, the encryption table is searched through and the data code pairing with the encryption code is outputted to the second region, and when the data code is stored in the second region, the encryption table is searched through and the encryption code paring with the data code is outputted to the first region; a reception section that receives from outside a command code and the encryption code; and a transmission section that transmits outside the encryption code, wherein, upon receiving from outside a write command as the command code and the encryption code at the reception section, the encryption code r

Abstract: A program execution device includes: a lookup table storage section that stores a lookup table stipulating a plurality of relations between a plurality of input data and a plurality of output data that are results of operation conducted on the plurality of input data; a program storage section that stores a program including a command directing to obtain one of the output data that is a result of the operation conducted on one of the input data, which is defined by the one of the input data and the operation; and a program execution section having a first cycle of designating the one of the input data in the command to the lookup table in the lookup table storage section, and a second cycle of receiving the one of the output data corresponding to the one of the input data from the lookup table.

Abstract: A storage device includes: a ferroelectric memory that temporarily stores data, wherein the ferroelectric memory stores an error correction code that is used for verifying the data by correcting errors possibly occurring on the data stored; a storage medium that has a plurality of storage regions and continually stores the data in one of the plurality of storage regions; and a control section that (1) writes the data and the error correction code to the ferroelectric memory, (2) writes the data written in the ferroelectric memory to one of the storage regions in the storage medium, (3) compares the data that is written in the ferroelectric memory and has been verified by using the error correction code written in the ferroelectric memory with the data written to the one of the storage regions in the storage medium, and (4) rewrites the data that has been verified to another one of the storage regions in the storage medium when both of the data do not match each other.

Abstract: An encryption processing circuit includes: a rewritable ferroelectric memory including an encryption table containing one or more data codes paired with encryption codes that are the data codes encrypted, a first region for storing the encryption codes, and a second region for storing the data codes, wherein, when the encryption code is stored in the first region, the encryption table is searched through and the data code pairing with the encryption code is outputted to the second region, and when the data code is stored in the second region, the encryption table is searched through and the encryption code paring with the data code is outputted to the first region.

Abstract: A display allowing further miniaturization when including a plurality of display panels is obtained. This display comprises a first display panel formed on a substrate and a second display panel formed on the same substrate on a region different from that formed with the first display panel. Thus, the display can be further miniaturized as compared with that having a first display panel and a second display panel formed on different substrates.

Abstract: A digital image signal is serially transferred to each of pixels through a drain signal line. The digital image signal is sampled at pixel selecting transistors, converted from a serial signal to a parallel signal, and then converted to an analog image signal by a DA converter. This DA converter includes a plurality of capacitor electrodes coupled to a pixel electrode at a weighted capacitance ratio and a clock supplying portion for supplying periodic clock signals to the plurality of the capacitor electrodes in response to the digital image signal. The analog image signal is applied to the pixel electrode. This simplifies a configuration of peripheral circuits of the pixel, and accordingly reduces the frame area of a panel and the number of wiring lines.

Abstract: A display apparatus includes a video signal processing unit, a display panel, and a bidirectional bus. The video signal processing unit transmits a video signal via the bidirectional bus. The display panel displays an image in accordance with the video signal. The video signal processing unit and the display module are connected to the bidirectional bus. When a tester is connected to the bidirectional bus, the bidirectional bus directly connects the tester to the video signal processing unit and the display module. The tester separately tests the video signal processing unit and the display panel after the display apparatus is assembled.

Abstract: A display module enabling recognition of an image when the entire screen is bright (or dark). A current drive circuit includes a current amount control circuit for controlling the amount of current supplied from a high potential power supply to a transmission path in response to a current control signal. A drive current generation circuit controls the amount of current flowing through a transmission line in accordance with a gray scale value of video data based on RGB pulse width modulation signals. Current, which corresponds to the difference between the current of the current amount control circuit and the current controlled by the drive current generation circuit, flows through the transmission line. When using the drive current of the drive current generation circuit as a base current, the current amount control circuit adds current to the drive current with the current control signal.

Abstract: A number of data transmission lines between a controller LSI and a display device and external devices is reduced to reduce a wiring space in a portable information device to realize further size reduction of the device. A controller LSI side transmission/reception circuit is included in the controller LSI, while an external device selection and transmission circuit and a display unit are included in a display device. And two-way transmission lines are provided between the controller LSI side transmission/reception circuit and the external device selection and transmission circuit. Various kinds of external devices MD0-MD3 for human interface are connected to the external device selection and transmission circuit.

Abstract: This invention enables the image data transmission with high frequency without having the EMI noise or the deterioration of SN ratio. The image data SR is inputted to the electric current driving circuit 30 after it is modulated into the pulse width modulation signal SRP by the pulse width modulation circuit 10. The electric current driving circuit 30 outputs the first and the second driving electric current I1, I2 to the transmission lines 41, 42 based on the pulse width modulation signal SRP. The first and the second driving electric currents I1 and I2 have the same magnitude but the opposite directions. The pixels GS1 and GS2 with the electric current driven luminescent element L1 and L are driven by the first and second driving electric currents I1 and I2.

Abstract: The variation of the electric current fed to the luminescent element is prevented in the display device with the electric current driven luminescent element, achieving uniform display brightness. The pulse width modulation circuit 10 generating a pulse width modulation signal SRP, the pulse of which is modulated for a certain period according to the image data, and the electric current generation circuit 20 generating the pulse current I corresponding the pulse width modulation signal are formed. The pulse current I is supplied to the electric current driven luminescent elements L1 and L2 through the pixel selection TFT 51, 52. Since the pulse current I is stable and at a certain level, it is not influenced by the variation among the pixels due to the manufacturing process, achieving uniform display brightness and improved display quality.

Abstract: A digital image signal is serially transferred to each of pixels through a drain signal line. The digital image signal is sampled at pixel selecting transistors, converted from a serial signal to a parallel signal, and then converted to an analog image signal by a DA converter. This DA converter includes a plurality of capacitor electrodes coupled to a pixel electrode at a weighted capacitance ratio and a clock supplying portion for supplying periodic clock signals to the plurality of the capacitor electrodes in response to the digital image signal. The analog image signal is applied to the pixel electrode. This simplifies a configuration of peripheral circuits of the pixel, and accordingly reduces the frame area of a panel and the number of wiring lines.

Abstract: A display allowing further miniaturization when including a plurality of display panels is obtained. This display comprises a first display panel formed on a substrate and a second display panel formed on the same substrate on a region different from that formed with the first display panel. Thus, the display can be further miniaturized as compared with that having a first display panel and a second display panel formed on different substrates.

Abstract: A package is provided for achieving higher packing density and higher circuit integration of memories, in particular, a structure is provided having a plurality of thin, surface mount packages which are stacked up. Each of the laminated packages includes a semiconductor pellet, leads fixed to the front surface of the pellet, a radiating plate fixed to the rear surface of the same, and a resin mold member. To achieve a stabilized laminated structure, the mold member is shaped into a convex form on the front side of the pellet and into a concave form on the rear side of the same, so that the concave portion of one package can engage with the convex portion of another package.

Abstract: In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained.

Abstract: In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained.