Abstract: A mode selection arrangement for use in a timer includes a gear box and a printed circuit board provided at the back of the gear box. Predetermined contact patterns are formed on a face of the printed circuit board facing the gear box. Rotatably provided in the gear box are display gears and switch gears. Each display gear has a plurality of indicia depicted on its face, and the corresponding switch gear rotates operatively or integrally with the display gear. A sliding contact member is fixedly attached to each switch gear, so that the sliding contact member slidingly contacts the corresponding contact pattern. A front plate having windows formed therein is provided to close the gear box so that the indicia are displayed through the windows.

Abstract: An electronic timer with a case having two windows and a manually adjustable control on the exterior. The output of an oscillator within the case is applied to a first frequency divider dividing the frequency by a factor manually selected by a switch indicating the factor in one window. The output of the first divider is applied to a second divider dividing by a factor selected manually by a second switch viewable through the other window and indicating timing in seconds, minutes, hours or days.

Abstract: An electronic timer having an oscillator, a counter which counts outputs of the oscillator up to a predetermined count value and thereupon generates an output, and an output circuit for generating an output signal in response to the output from the counter, the oscillator comprisinga first terminal for connection with a time constant circuit consisting of a resistor and a capacitor,a second terminal supplied with a reference voltage,a dividing resistance circuit for developing a first upper limit voltage and a lower limit voltage,a first upper limit comparator for comparing a potential at the first terminal with the first upper limit voltage,a second upper limit comparator for comparing the potential at first terminal with the reference voltage,an OR-circuit for receiving outputs from the first and second upper limit comparators,a lower limit comparator for comparing the potential at the first terminal with the lower limit voltage,a flip-flop which is set by an output from the OR-circuit and reset by an outpu