Patents by Inventor Isao Fujisawa

Isao Fujisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456023
    Abstract: There is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 27, 2022
    Assignee: Kioxia Corporation
    Inventors: Yutaka Shimizu, Satoshi Inoue, Isao Fujisawa, Yumi Takada
  • Publication number: 20210335401
    Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.
    Type: Application
    Filed: December 14, 2020
    Publication date: October 28, 2021
    Applicant: Kioxia Corporation
    Inventors: Yutaka SHIMIZU, Satoshi INOUE, Isao FUJISAWA, Yumi TAKADA
  • Patent number: 6097228
    Abstract: A semiconductor integrated circuit device includes an MCU, reset circuit and reset input circuit. The reset circuit resets the MCU in response to a reset signal input to a reset terminal. The reset input circuit eliminates an electromagnetic disturbance noise input to the reset terminal, permits only a signal having an effective pulse width to pass therethrough, forms an internal reset signal of a pulse width required for the reset operation according to the signal, and supplies the same to the reset circuit. The reset input circuit includes an analog delay circuit, delay latch group, effective pulse width detection circuit and waveform forming circuit. The analog delay circuit eliminates a noise of a period shorter than the effective pulse width from the reset signal. The delay latch group sequentially samples an output signal of the analog delay circuit.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: August 1, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Fujisawa, Yoshikazu Nagashima, Nobutaka Kitagawa
  • Patent number: 4926166
    Abstract: A display circuit for driving two or more different displays includes a display memory for storing display data, an address signal generation circuit for generating address signals for the display memory, basic timing generation circuit for generating basic timing signals, an address control circuit for controlling a determination of the address of the display memory along the horizontal- and vertical-direction of the displays, and a switching circuit for switching the horizontal- and vertical-direction timing signals depending upon which one of the two or more display is selected, whereby the two or more displays are independently operated.
    Type: Grant
    Filed: April 16, 1985
    Date of Patent: May 15, 1990
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Isao Fujisawa, Katsuhiko Hashimoto
  • Patent number: 4192060
    Abstract: In an electronic calculator essentially comprising a multidigit display, a keyboard and a data processor unit, a multidigit liquid crystal display is deposited together with integral key actuators of the keyboard of a flexible circuit film which carries electrical conductor leaves in a desired pattern. The conductor leaves to be in contact with terminals of the liquid crystal display are formed to extend in the direction of length of the liquid crystal display to thereby establish room for a battery compartment.
    Type: Grant
    Filed: December 21, 1977
    Date of Patent: March 11, 1980
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Isamu Washizuka, Shintaro Hashimoto, Masaru Kakumae, Yuuichi Sato, Isao Fujisawa, Yukihiro Inoue, Sadakatsu Hashimoto
  • Patent number: 4104727
    Abstract: In an electronic calculator essentially comprising a multidigit display, a keyboard and a data processor unit, a multidigit liquid crystal display is deposited together with integral key actuators of the keyboard on a flexible circuit film which carries electrical conductor leaves in a desired pattern. The conductor leaves to be in contact with terminals of the liquid crystal display are formed to extend in the direction of length of the liquid crystal display to thereby establish room for a battery compartment.
    Type: Grant
    Filed: September 23, 1976
    Date of Patent: August 1, 1978
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Isamu Washizuka, Shintaro Hashimoto, Masaru Kakumae, Yuuichi Sato, Isao Fujisawa, Yukihiro Inoue, Sadakatsu Hashimoto, Yoshio Takeda, Mitsuo Ishii, Yoshitomo Kitanishi