Abstract: An address setting and filtering system for terminal accommodating circuits in packet switching systems for detecting and registering the address set by a terminal unit. The address system also prevents double registration of addresses. In one form of the invention, a source address detecting circuit detects and outputs an orginating source address from a source packet frame which is stored in a terminal address memory as a terminal source address. An address filter extracts a destination address from a packet frame received. If the destination address and the terminal address are the same, the received packet frame is transferred to the terminal unit.

Abstract: In a common bus control method, transmission and reception buses are connected to a unit having a unit number 1. A synchronization frame head signal for time-division slots of common buses is sequentially supplied to the units in the order of the unit numbers 1 to n through delay circuits. Phase correcting circuits are respectively connected to the transmission and reception buses of each unit so as to perform phase correction of data on the buses and latch signals for latching the data. The delay circuit arranged in each unit sets transmission delay data having an inherent delay difference on the basis of the synchronization frame head signal. An output from the delay circuit of each unit is used as the latch signal.