Patents by Inventor Isao Miyazaki

Isao Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7304001
    Abstract: Under the condition that a semiconductor maker and a photomask maker are separated but these are mutually connected with a communication line, the semiconductor maker gives a photomask fabrication schedule information to the photomask maker via the communication line, while the photomask maker fabricates the photomask depending on such fabrication schedule information and delivers the photomask to the semiconductor maker. The photomask maker periodically sends, in the course of fabrication process, a photomask fabrication progress information to the semiconductor maker via the communication line. The semiconductor maker regenerates the photomask fabrication schedule information depending on the photomask fabrication progress information sent from the photomask maker and then transfers the re-generated photomask fabrication schedule information to the photomask maker via the communication line.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: December 4, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Isao Miyazaki, Yasushi Takeuchi, Toshihiro Morii, Koji Sekiguchi, Yoshihiko Okamoto
  • Publication number: 20070248951
    Abstract: Disclosed herein are a determination method capable of determining the presence or absence of an anti-HIV antibody in a sample with accuracy even if an operation of cleaning is omitted and a determination kit to be used for the determination method. The determination method is as follows. First, a liquid specimen containing a sample obtained from a living body is fed into a well carrying a HIV antigen on an inner surface thereof. Next, a reagent containing colored particles carrying an anti-IgG antibody is fed into the well. Then in a case where the anti-IgG antibody is bound to the anti-HIV antibody which has been bound to the HIV antigen so that the particles are dispersed in the well, the sample is positive, while that in a case where the particles are precipitated and agglutinated in the well, the sample is negative.
    Type: Application
    Filed: October 19, 2006
    Publication date: October 25, 2007
    Applicant: PENTAX Corporation
    Inventors: Kazumi YAGASAKI, Isao MIYAZAKI
  • Publication number: 20070141596
    Abstract: Disclosed herein are a plate capable of determining the presence or absence of an anti-virus antibody with higher accuracy, a determination kit equipped with the plate, and a determination method using the determination kit for immunoassay. The determination method is as follows. First, a liquid specimen is fed into each of the predetermined wells of the plate fixed two or more kinds of antigens derived from a specific virus. Each well carries one of the two or more kinds of antigens on the inner surface thereof. Then, a reagent containing colored particles 1 carrying an anti-IgG antibody is fed into each of the wells containing the liquid specimen. When an antibody bound to the antigen is detected in a predetermined number or more of the wells, a living body is determined to be infected with the virus.
    Type: Application
    Filed: October 19, 2006
    Publication date: June 21, 2007
    Applicant: PENTAX CORPORATION
    Inventors: Kazumi Yagasaki, Isao Miyazaki
  • Patent number: 7052842
    Abstract: A method for hybridizing nucleic acids, which includes an annealing step of preparing a first single stranded nucleic acid fragment immobilized on a surface of an immobilizing material and a second single stranded nucleic acid fragment labeled with fluorescence or radioisotope and forming a complementary double strand from the first single stranded nucleic acid fragment and the second single stranded nucleic acid fragment, and an enzyme treatment step. In the annealing step, the complementary double strand is formed by performing a temperature gradient processing performed from a high temperature area to a low temperature area, and in the enzyme treatment step, a noncomplementary nucleic acid portion contained in the complementary double stand is recognized and cleaved by adding endonuclease. This method has high measurement sensitivity and the operation is simple.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: May 30, 2006
    Assignee: NGK Insulators, Ltd.
    Inventors: Mitsuo Kawase, Kazunari Yamada, Isao Miyazaki, Chiho Matsuda
  • Patent number: 6757621
    Abstract: A process management system in accordance with the present invention includes inspection apparatuses for inspecting defects on a wafer, the inspection apparatuses being connected through a communication network, inspection information and image information obtained from these inspection apparatuses being collected to construct a data base and an image file, therein definition of defects is given by combinations of elements which characterize the defect based on the inspection information and the image information obtained from the inspection apparatuses. By giving definition of the defect, characteristics of the defect can be subdivided and known. Therefore, the cause of a defect can be studied.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: June 29, 2004
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Fumio Mizuno, Seiji Isogai, Kenji Watanabe, Yasuhiro Yoshitake, Terushige Asakawa, Yuichi Ohyama, Hidekuni Sugimoto, Seiji Ishikawa, Masataka Shiba, Jun Nakazato, Makoto Ariga, Tetsuji Yokouchi, Toshimitsu Hamada, Ikuo Suzuki, Masami Ikota, Mari Nozoe, Isao Miyazaki, Yoshiharu Shigyo
  • Publication number: 20030186266
    Abstract: A method for hybridizing nucleic acids, which includes an annealing step of preparing a first single stranded nucleic acid fragment immobilized on a surface of an immobilizing material and a second single stranded nucleic acid fragment labeled with fluorescence or radioisotope and forming a complementary double strand from the first single stranded nucleic acid fragment and the second single stranded nucleic acid fragment, and an enzyme treatment step. In the annealing step, the complementary double strand is formed by performing a temperature gradient processing performed from a high temperature area to a low temperature area, and in the enzyme treatment step, a noncomplementary nucleic acid portion contained in the complementary double stand is recognized and cleaved by adding endonuclease. This method has high measurement sensitivity and the operation is simple.
    Type: Application
    Filed: October 23, 2002
    Publication date: October 2, 2003
    Inventors: Mituso Kawase, Kazunari Yamada, Isao Miyazaki, Chiho Matsuda
  • Patent number: 6628817
    Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: September 30, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Ishikawa, Masao Sakata, Jun Nakazato, Sadao Shimoyashiro, Hiroto Nagatomo, Yuzo Taniguchi, Osamu Satou, Tsutomu Okabe, Yuzaburo Sakamoto, Kimio Muramatsu, Kazuhiko Matsuoka, Taizo Hashimoto, Yuichi Ohyama, Yutaka Ebara, Isao Miyazaki, Shuichi Hanashima
  • Publication number: 20030130806
    Abstract: A process management system in accordance with the present invention includes inspection apparatuses for inspecting defects on a wafer, the inspection apparatuses being connected through a communication network, inspection information and image information obtained from these inspection apparatuses being collected to construct a data base and an image file, therein definition of defects is given by combinations of elements which characterize the defect based on the inspection information and the image information obtained from the inspection apparatuses. By giving definition of the defect, characteristics of the defect can be subdivided and known. Therefore, the cause of a defect can be studied.
    Type: Application
    Filed: January 16, 2003
    Publication date: July 10, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Fumio Mizuno, Seiji Isogai, Kenji Watanabe, Yasuhiro Yoshitake, Terushige Asakawa, Yuichi Ohyama, Hidekuni Sugimoto, Seiji Ishikawa, Masataka Shiba, Jun Nakazato, Makoto Ariga, Tetsuji Yokouchi, Toshimitsu Hamada, Ikuo Suzuki, Masami Ikota, Mari Nozoe, Isao Miyazaki, Yoshiharu Shigyo
  • Patent number: 6542830
    Abstract: A process management system in accordance with the present invention includes inspection apparatuses for inspecting defects on a wafer, the inspection apparatuses being connected through a communication network, inspection information and image information obtained from these inspection apparatuses being collected to construct a data base and an image file, therein definition of defects is given by combinations of elements which characterize the defect based on the inspection information and the image information obtained from the inspection apparatuses. By giving definition of the defect, characteristics of the defect can be subdivided and known. Therefore, the cause of a defect can be studied.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: April 1, 2003
    Assignees: Hitachi, Ltd., Hitachi Instruments Engineering Co., Ltd.
    Inventors: Fumio Mizuno, Seiji Isogai, Kenji Watanabe, Yasuhiro Yoshitake, Terushige Asakawa, Yuichi Ohyama, Hidekuni Sugimoto, Seiji Ishikawa, Masataka Shiba, Jun Nakazato, Makoto Ariga, Tetsuji Yokouchi, Toshimitsu Hamada, Ikuo Suzuki, Masami Ikota, Mari Nozoe, Isao Miyazaki, Yoshiharu Shigyo
  • Publication number: 20030056189
    Abstract: Under the condition that a semiconductor maker and a photomask maker are separated but these are mutually connected with a communication line, the semiconductor maker gives a photomask fabrication schedule information to the photomaskmaker via the communication line, while the photomask maker fabricates the photomask depending on such fabrication schedule information and delivers the photomask to the semiconductor maker. The photomask maker periodically sends, in the course of fabrication process, a photomask fabrication progress information to the semiconductor maker via the communication line. The semiconductor maker regenerates the photomask fabrication schedule information depending on the photomask fabrication progress information sent from the photomask maker and then transfers the re-generated photomask fabrication schedule information to the photomask maker via the communication line.
    Type: Application
    Filed: August 21, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi Ltd.
    Inventors: Isao Miyazaki, Yasushi Takeuchi, Toshihiro Morii, Koji Sekiguchi, Yoshihiko Okamoto
  • Patent number: 6529619
    Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: March 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Ishikawa, Masao Sakata, Jun Nakazato, Sadao Shimoyashiro, Hiroto Nagatomo, Yuzo Taniguchi, Osamu Satou, Tsutomu Okabe, Yuzaburo Sakamoto, Kimio Muramatsu, Kazuhiko Matsuoka, Taizo Hashimoto, Yuichi Ohyama, Yutaka Ebara, Isao Miyazaki, Shuichi Hanashima
  • Patent number: 6404911
    Abstract: A semiconductor failure analysis system and method therefor facilitated by a failure information collection unit for collection, by bit, failure information of a semiconductor, an inspection unit for examining relations between various types of inspection data obtained by inspection of the semiconductor and for examining relations between the inspection data and failure information, a storage unit for storing design information of the semiconductor, an analysis unit for analyzing the failure information from the failure information collection unit, from the inspection unit and design information stored in the storage unit, a display unit for displaying at least one of the result of analysis from the analysis unit and the failure information, a failure cause estimation unit for estimating a cause of the failure information, and a unit for feeding the estimated cause of the failure information back to a process in which the failure has occurred.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 11, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazuko Ishihara, Seiji Ishikawa, Masao Sakata, Isao Miyazaki, Yoshiyuki Miyamoto, Jun Nakazato
  • Publication number: 20020034326
    Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.
    Type: Application
    Filed: October 30, 2001
    Publication date: March 21, 2002
    Inventors: Seiji Ishikawa, Masao Sakata, Jun Nakazato, Sadao Shimoyashiro, Hiroto Nagatomo, Yuzo Taniguchi, Osamu Satou, Tsutomu Okabe, Yuzaburo Sakamoto, Kimio Muramatsu, Kazuhiko Matsuoka, Taizo Hashimoto, Yuichi Ohyama, Yutaka Ebara, Isao Miyazaki, Shuichi Hanashima
  • Patent number: 6339653
    Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: January 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Ishikawa, Masao Sakata, Jun Nakazato, Sadao Shimoyashiro, Hiroto Nagatomo, Yuzo Taniguchi, Osamu Satou, Tsutomu Okabe, Yuzaburo Sakamoto, Kimio Muramatsu, Kazuhiko Matsuoka, Taizo Hashimoto, Yuichi Ohyama, Yutaka Ebara, Isao Miyazaki, Shuichi Hanashima
  • Patent number: 6330352
    Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: December 11, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Ishikawa, Masao Sakata, Jun Nakazato, Sadao Shimoyashiro, Hiroto Nagatomo, Yuzo Taniguchi, Osamu Satou, Tsutomu Okabe, Yuzaburo Sakamoto, Kimio Muramatsu, Kazuhiko Matsuoka, Taizo Hashimoto, Yuichi Ohyama, Yutaka Ebara, Isao Miyazaki, Shuichi Hanashima
  • Publication number: 20010038708
    Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.
    Type: Application
    Filed: June 29, 2001
    Publication date: November 8, 2001
    Inventors: Seiji Ishikawa, Masao Sakata, Jun Nakazato, Sadao Shimoyashiro, Hiroto Nagatomo, Yuzo Taniguchi, Osamu Satou, Tsutomu Okabe, Yuzaburo Sakamoto, Kimio Muramatsu, Kazuhiko Matsuoka, Taizo Hashimoto, Yuichi Ohyama, Yutaka Ebara, Isao Miyazaki, Shuichi Hanashima
  • Patent number: 6272917
    Abstract: A draw-false twisting management system that measures untwisting tension with an untwisting tension sensor (13) and diagnoses trouble in a draw-false twisting machine, wherein the measured values are subjected to fast Fourier transform online by fast Fourier transform means (18), the untwisting tension signal is monitored in a frequency domain, a pattern is extracted for the integral value (area value) or peak value in a specific frequency band, and a comparative judgment against a preset reference pattern is made by trouble-judging means (19), which judges that trouble has occurred in the draw-false twisting when the value falls outside of the reference value range.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: August 14, 2001
    Assignee: Teijin Limited
    Inventors: Bunji Hamasu, Katsushi Kikuchi, Isao Miyazaki
  • Publication number: 20010001015
    Abstract: The present invention provides data analysis stations respectively for a probing tester and an automatic particle inspection machine. And, in the data analysis station, the coordinates on which the disposition of the chips are described on a product basis are equal to those on which the locations of the defects are described. Further, the station provides a function of determining which of the chips each defect belongs to. These data analysis stations are connected through a communication line. The present invention is capable of analyzing the data on a chip basis, resulting in being able to grasp the relation between how the defects are caused on each chip and the product character of the chip.
    Type: Application
    Filed: January 3, 2001
    Publication date: May 10, 2001
    Inventors: Seiji Ishikawa, Masao Sakata, Jun Nakazato, Sadao Shimoyashiro, Hiroto Nagatomo, Yuzo Taniguchi, Osamu Satou, Tsutomu Okabe, Yuzaburo Sakamoto, Kimio Muramatsu, Kazuhiko Matsuoka, Taizo Hashimoto, Yuichi Ohyama, Yutaka Ebara, Isao Miyazaki, Shuichi Hanashima
  • Publication number: 20010000460
    Abstract: A semiconductor failure analysis system which includes a failure information collection unit for collecting, by bit, failure information concerned with a failure of a semiconductor, an inspection unit for examining relations between various types of inspection data obtained by inspection of the semiconductor and for examining relations between said inspection data and the failure information, a storage unit for storing information concerned with design of said semiconductor, an analysis unit for analyzing the failure information on the basis of output information output from the failure information collection unit, output information output from the inspection unit and design information stored in the storage unit, a display unit for displaying at least one of the result of analysis output from the analysis unit and the failure information, a failure cause estimation unit for estimating a cause of said failure information, and an unit for feeding the estimated cause of said failure information back to a proce
    Type: Application
    Filed: December 8, 2000
    Publication date: April 26, 2001
    Inventors: Kazuko Ishihara, Seiji Ishikawa, Masao Sakata, Isao Miyazaki, Yoshiyuki Miyamoto, Jun Nakazato
  • Patent number: 6185324
    Abstract: A semiconductor failure analysis system which includes a failure information collection unit for collecting, by bit, failure information concerned with a failure of a semiconductor, an inspection unit for examining relations between various types of inspection data obtained by inspection of the semiconductor and for examining relations between said inspection data and the failure information, a storage unit for storing information concerned with design of said semiconductor, an analysis unit for analyzing the failure information on the basis of output information output from the failure information collection unit, output information output from the inspection unit and design information stored in the storage unit, a display unit for displaying at least one of the result of analysis output from the analysis unit and the failure information, a failure cause estimation unit for estimating a cause of said failure information, and an unit for feeding the estimated cause of said failure information back to a proce
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: February 6, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Kazuko Ishihara, Seiji Ishikawa, Masao Sakata, Isao Miyazaki, Yoshiyuki Miyamoto, Jun Nakazato