Patents by Inventor Isao Nagayoshi

Isao Nagayoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240054083
    Abstract: A semiconductor device capable of shortening processing time of a neural network is provided. The memory stores a compressed weight parameter. A plurality of multiply accumulators perform a multiply-accumulation operation to a plurality of pixel data and a plurality of weight parameters. A decompressor restores the compressed weight parameter stored in the memory to a plurality of weight parameters. A memory for weight parameter stores the plurality of weight parameters restored by the decompressor. The DMA controller transfers the plurality of weight parameters from the memory to the memory for weight parameter via the decompressor. A sequence controller writes down the plurality of weight parameters stored in the memory for weight parameter to a weight parameter buffer at write timing.
    Type: Application
    Filed: June 16, 2023
    Publication date: February 15, 2024
    Inventors: Kazuaki TERASHIMA, Isao NAGAYOSHI, Atsushi NAKAMURA
  • Patent number: 11763417
    Abstract: The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: September 19, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuaki Terashima, Isao Nagayoshi, Atsushi Nakamura
  • Publication number: 20220398441
    Abstract: A semiconductor device executes the processing of a neural network. The memory MEM1 holds a plurality of pixel values and j compressed weighting factors. The decompressor DCMP restores the j compressed weighting factors to the uncompressed k (k?j) weighting factors. The DMA controller DMAC1 reads the j compressed weighting factors from the memory MEM1 and transfers them to the decompressor DCMP. The n (n>k) accumulators in the accumulator unit ACCU multiply a plurality of pixel values and k uncompressed weighting factor to accumulate and add the multiplication results to the time series. A switch circuit SW1 provided between the decompressor DCMP and the accumulator unit ACCU transfers the k uncompressed weighting factors restored by the decompressor DCMP to n accumulators based on the correspondence represented by the identifier.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 15, 2022
    Inventors: Kazuaki TERASHIMA, Isao NAGAYOSHI, Atsushi NAKAMURA
  • Patent number: 9959221
    Abstract: A semiconductor device (100) according to an embodiment calculates the number of times of burst access for an address set (A) based on a result of a determination, for each of N addresses a1 to an (N is a natural number no less than two) included in the address set (A), whether or not the address and another address adjacent to that address in an accessing order can be accessed by the same burst access, and calculates an access time that will be taken for accessing the address set by the burst access.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 1, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Isao Nagayoshi
  • Publication number: 20160180918
    Abstract: A semiconductor device (100) according to an embodiment calculates the number of times of burst access for an address set (A) based on a result of a determination, for each of N addresses a1 to an (N is a natural number no less than two) included in the address set (A), whether or not the address and another address adjacent to that address in an accessing order can be accessed by the same burst access, and calculates an access time that will be taken for accessing the address set by the burst access.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 23, 2016
    Inventor: Isao NAGAYOSHI
  • Publication number: 20060171463
    Abstract: Herein disclosed is a bit stream separating and merging system comprising a bit stream separating apparatus (1000) for inputting and transcoding an original bit stream A to separate into and generate a base bit stream B and one or more extended differential bit streams E*, each having a partial differential information segment between the original bit stream A and the base bit stream B, and a bit stream merging apparatus (2000) for inputting and merging the base bit stream B and the one or more extended differential bit streams E* to reconstruct the original bit stream A or a pseudo original bit stream B* approximately similar to the original bit stream A.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 3, 2006
    Applicant: Media Glue Corporation
    Inventors: Tsuyoshi Hanamura, Isao Nagayoshi, Hideyoshi Tominaga
  • Publication number: 20050271140
    Abstract: Herein disclosed is a multiple-output bit stream separating apparatus for inputting an original MPEG-2 bit stream to separate into a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams, and a multiple-output bit stream merging apparatus for inputting the transcoded MPEG-2 bit stream and the differential bit streams to reconstruct the original MPEG-2 bit stream. The bit rate of the transcoded MPEG-2 bit stream and the differential bit streams thus multiple times separated are much lower than that of the original MPEG-2 bit stream. This leads to the fact that the multiple-output bit stream separating apparatus and the multiple-input bit stream merging apparatus can promptly and reliably transmit and receive an original MPEG-2 bit stream having a large bit rate by transmitting and receiving a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams in place of the original MPEG-2 bit stream.
    Type: Application
    Filed: May 23, 2005
    Publication date: December 8, 2005
    Inventors: Tsuyoshi Hanamura, Isao Nagayoshi, Hiroyuki Kasai, Hideyoshi Tominaga
  • Patent number: 6901109
    Abstract: Herein disclosed is a multiple-output bit stream separating apparatus for inputting an original MPEG-2 bit stream to separate into a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams, and a multiple-output bit stream merging apparatus for inputting the transcoded MPEG-2 bit stream and the differential bit streams to reconstruct the original MPEG-2 bit stream. The bit rate of the transcoded MPEG-2 bit stream and the differential bit streams thus multiple times separated are much lower than that of the original MPEG-2 bit stream. This leads to the fact that the multiple-output bit stream separating apparatus and the multiple-input bit stream merging apparatus can promptly and reliably transmit and receive an original MPEG-2 bit stream having a large bit rate by transmitting and receiving a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams in place of the original MPEG-2 bit stream.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: May 31, 2005
    Assignee: Media Glue Corporation
    Inventors: Tsuyoshi Hanamura, Isao Nagayoshi, Hiroyuki Kasai, Hideyoshi Tominaga
  • Patent number: 6895052
    Abstract: Herein disclosed a bit stream separating apparatus for inputting and transcoding an original MPEG-2 bit stream, and separating the transcoded MPEG-2 bit stream to generate a transcoded MPEG-2 bit stream and a differential bit stream, which is a differential bit stream between the original MPEG-2 bit stream and the transcoded MPEG-2 bit stream, and a bit stream merging apparatus for inputting and merging the transcoded MPEG-2 bit stream and the differential bit stream to reconstruct the original MPEG-2 bit stream. The bit stream separating apparatus makes it possible for the bit stream merging apparatus to reconstruct the original, high quality, MPEG-2 bit stream from the transcoded MPEG-2 bit stream already received and the differential bit stream, thereby eliminating the effort and time to send the original MPEG-2 bit stream again.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: May 17, 2005
    Inventors: Tsuyoshi Hanamura, Isao Nagayoshi, Hiroyuki Kasai, Hideyoshi Tominaga
  • Publication number: 20050100091
    Abstract: A coded signal separating apparatus, coded signal merging apparatus, coded signal separating and merging system, and methods thereof capable of performing scalable transmission of images are provided. There are provided a separating unit 1100, which is a separator separating means for separating a coded stream into a basic coded signal B having a smaller code amount than the coded stream and a plurality of extended coded signals E(m), which are used with the basic coded signal B to reconstruct an image, and a multiplexing unit 1600, which is a separator multiplexing means for optionally combining and multiplexing the basic coded signal B with the plurality of extended coded signals E(m) to generate a plurality of transmission coded signals St(1), to thereby generate and output separated streams St(1), which are multiplexed transmission coded signals.
    Type: Application
    Filed: November 10, 2004
    Publication date: May 12, 2005
    Applicant: Media Glue Corporation
    Inventors: Tsuyoshi Hanamura, Isao Nagayoshi, Michiko Wakui, Hideyoshi Tominaga
  • Publication number: 20020094025
    Abstract: Herein disclosed is a multiple-output bit stream separating apparatus for inputting an original MPEG-2 bit stream to separate into a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams, and a multiple-output bit stream merging apparatus for inputting the transcoded MPEG-2 bit stream and the differential bit streams to reconstruct the original MPEG-2 bit stream. The bit rate of the transcoded MPEG-2 bit stream and the differential bit streams thus multiple times separated are much lower than that of the original MPEG-2 bit stream. This leads to the fact that the multiple-output bit stream separating apparatus and the multiple-input bit stream merging apparatus can promptly and reliably transmit and receive an original MPEG-2 bit stream having a large bit rate by transmitting and receiving a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams in place of the original MPEG-2 bit stream.
    Type: Application
    Filed: November 27, 2001
    Publication date: July 18, 2002
    Inventors: Tsuyoshi Hanamura, Isao Nagayoshi, Hiroyuki Kasai, Hideyoshi Tominaga
  • Publication number: 20020054638
    Abstract: Herein disclosed a bit stream separating apparatus for inputting and transcoding an original MPEG-2 bit stream, and separating the transcoded MPEG-2 bit stream to generate a transcoded MPEG-2 bit stream and a differential bit stream, which is a differential bit stream between the original MPEG-2 bit stream and the transcoded MPEG-2 bit stream, and a bit stream merging apparatus for inputting and merging the transcoded MPEG-2 bit stream and the differential bit stream to reconstruct the original MPEG-2 bit stream. The bit stream separating apparatus makes it possible for the bit stream merging apparatus to reconstruct the original, high quality, MPEG-2 bit stream from the transcoded MPEG-2 bit stream already received and the differential bit stream, thereby eliminating the effort and time to send the original MPEG-2 bit stream again.
    Type: Application
    Filed: August 17, 2001
    Publication date: May 9, 2002
    Inventors: Tsuyoshi Hanamura, Isao Nagayoshi, Hiroyuki Kasai, Hideyoshi Tominaga