Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

Abstract: A semiconductor device capable of reducing a fabrication period as well as a fabrication cost when timing control for signal transmission is necessary is obtained. This semiconductor device comprises a first semiconductor chip consisting of at least either a circuit against static damage or a passive component. When a plurality of semiconductor chips installed on a support substrate are connected with each other through the first semiconductor chip, timing control for signal transmission is enabled by simply modifying the first semiconductor chip. In this case, the first semiconductor chip having a relatively simple structure can be modified in a shorter time at a lower cost as compared with a case of re-forming a semiconductor chip having an individual function. Thus, the modification period as well as the modification cost can be reduced when timing control for signal transmission is necessary.

Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

Abstract: A plurality of first basic cells and a plurality of second basic cells are formed on a semiconductor substrate. A gate electrode of each of transistors in the first basic cell has a gate length of the minimum size. A gate electrode of each of transistors in the second basic cell has a second gate length larger than the first gate length. The transistors in the first basic cell are connected to each other, to construct a circuit which is operable at high speed and can be increased in integration density. The transistors in the second basic cell are connected to each other, to construct a circuit which can be reduced in power consumption and is hardly affected by process variations.

Abstract: A semiconductor device capable of reducing a fabrication period as well as a fabrication cost when timing control for signal transmission is necessary is obtained. This semiconductor device comprises a first semiconductor chip consisting of at least either a circuit against static damage or a passive component. When a plurality of semiconductor chips installed on a support substrate are connected with each other through the first semiconductor chip, timing control for signal transmission is enabled by simply modifying the first semiconductor chip. In this case, the first semiconductor chip having a relatively simple structure can be modified in a shorter time at a lower cost as compared with a case of re-forming a semiconductor chip having an individual function. Thus, the modification period as well as the modification cost can be reduced when timing control for signal transmission is necessary.

Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.

Abstract: A basic cell has a plurality of transistors that are separated from one another for forming an electronic circuit that has a particular function when the transistors are coupled. The basic cell has at least two transistors. One is different in size and orientation from the other.