Patents by Inventor Isao Ota

Isao Ota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4704002
    Abstract: A dot matrix display panel with a thin film transistor and the manufacturing method therefor, the panel being so constructed that a gate insulating layer and a semiconductor layer are provided as one laminated film substantially equal in the size thereto on an insulating substrate having a gate electrode and in a region of the substrate except for the peripheral portion thereof, and a source electrode and a drain electrode come into contact with the semiconductor layer in a region covering the gate electrode and gate insulating layer so as to constitute a thin film transistor array substrate, so that a display medium is sandwiched between the array substrate and the substrate having a transparent electrode.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: November 3, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isako Kikuchi, Isao Ota, Mamoru Takeda, Seiji Kiyokawa
  • Patent number: 4496981
    Abstract: A video camera with a monitor, which is provided integrally on both surfaces or the same one surface of a semiconductor substrate or a substrate having a semiconductor film thereon; an image pickup plate and a display unit in one functioning as the image pickup plate for converting an optical image into an electrical signal and the display unit for converting the electrical signal into a visual image; the camera is provided with an optical system for imaging the optical image on the pickup plate.
    Type: Grant
    Filed: July 5, 1984
    Date of Patent: January 29, 1985
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Isao Ota
  • Patent number: 4332075
    Abstract: A method of producing thin film transistor arrays and having at least 7 steps including: a first step of forming a first electrode layer uniformly over an insulating substrate; a second step of forming electrodes, such as drain and source electrodes and bus bars with a desired pattern by photoetching the first electrode; a third step of forming a uniform semiconducting layer on the surface of the substrate having the patterned electrodes; a fourth step of successively forming a uniform insulating layer over the uniformly deposited semiconducting layer while keeping the array in a vacuum; a fifth step of photoetching the uniformly deposited insulating layer into a desired pattern; a sixth step of photoetching the uniform semiconducting layer into the same pattern as the patterned insulating layer; a seventh step of forming a second electrode uniformly over the surface having the patterned electrodes and insulating layer; and an eighth step of photoetching the uniformly deposited second electrode into a desired
    Type: Grant
    Filed: May 22, 1979
    Date of Patent: June 1, 1982
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Ota, Haruhiro Shirazawa, Toshio Tatsumichi, Hiroshi Kawarada, Tetsuro Ohtsuka