Patents by Inventor Ishita Satishchandra Desai

Ishita Satishchandra Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell write assist in response to voltage tracking of a replica circuit
    Patent number: 10861534
    Abstract: The claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. Particularly, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 8, 2020
    Assignee: Arm Limited
    Inventors: Ankur Goel, Ishan Khera, Nimish Sharma, Ishita Satishchandra Desai, Vikash Kumar, Nitesh Gautam
  • Memory Cell Write Assist in Response to Voltage Tracking of a Replica Circuit
    Publication number: 20200312403
    Abstract: Briefly, embodiments of claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. In particular embodiments, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Ankur Goel, Ishan Khera, Nimish Sharma, Ishita Satishchandra Desai, Vikash Kumar, Nitesh Gautam
  • Read-write architecture for low voltage SRAMs
    Patent number: 10790013
    Abstract: An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 29, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Prashant Dubey, Ishita Satishchandra Desai, Shivangi Mittal, Surya Prakash Gupta, Jamil Kawa