Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

Abstract: Apparatus and associated methods relate to compacting scan chain output responses of vectors into an on-chip multiple-input shift register (MISR) in the presence of unknown/indeterministic values X in design. In an illustrative example, a system may include a processing engine configured to generate a control signal for a MISR, and the control signal may hold information of what cycle has deterministic output response. The MISR may be configured to compact deterministic output responses of actual scan chain output responses in response to the decoded control signal and compare on-chip MISR signatures with expected MISR signatures to generate pass/fail status of the test. By using the system, unknown/indeterministic values X on the output responses may be blocked from being compacted into the MISR. Accordingly, the on-chip MISR signatures may not be corrupted by the unknown/indeterministic values X, and accuracy of the scan test may be advantageously improved.

Abstract: A disclosed integrated circuit includes first and second clock generation circuits, a stagger circuit, and a plurality of scan chains. The first clock generation circuit receives a first clock signal and generates a first set of clock pulses having a first frequency in response to receipt of a first clock trigger signal and a first enable signal. The second clock generation circuit receives a second clock signal and generates a second set of clock pulses having a second frequency in response to receipt of a second clock trigger signal and a second enable signal. The stagger circuit generates the first and second clock trigger signals from the global trigger signal at different times. The first set of clock pulses are staggered relative to the second set of clock pulses. The plurality of scan chains test functionality of logic circuitry within the IC chip using the first and second set of clock pulses.

Abstract: Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synchronizer and a controller. The controller is configured to initiate a clock stop process of the circuit by sending an alternative mode signal to the first synchronizer. The first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain and is further configured to output, to a select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock domain. The select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer for the clock of the first clock domain and an alternative clock input of the first clock multiplexer for an alternative clock signal from the controller.

Abstract: An integrated circuit (IC) structure can include an interposer including a plurality of inter-die wires and a first die coupled to the interposer. The first die can include a first output including a first flip-flop coupled to a first inter-die wire of the plurality of inter-die wires and a first input including a second flip-flop coupled to a second inter-die wire of the plurality of inter-die wires. The IC structure can include a second die coupled to the interposer. The second die can be configured with a first circuit design forming circuitry that couples the first inter-die wire to the second inter-die wire.

Abstract: Methods and systems generate a manufacturing test of a programmable integrated circuit and optionally test the programmable integrated circuit with the manufacturing test. A netlist is generated that represents a specific user design implemented in programmable resources of the programmable integrated circuit. The netlist represents user registers that are implemented in a portion of the logic registers of the programmable logic resources. A virtual scan chain is added to the netlist. Scan-test vectors are generated from the netlist using automatic test pattern generation (ATPG). The scan-test vectors serially scan the portion of the logic registers via the virtual scan chain. The scan-test vectors are converted into access-test vectors that access the portion of the logic registers via a configuration port of the programmable integrated circuit. The programmable integrated circuit is optionally tested for a manufacturing defect with the access-test vectors.

Abstract: An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.

Abstract: A circuit may be used for testing for faults in a programmable logic device. The circuit may include a clock generator coupled to receive a reference clock signal and generate a high speed clock signal; a circuit under test coupled to receive selected pulses of the high speed clock signal; and a programmable shift register coupled to receive a pulse width selection signal and generate an enable signal for selecting the pulses the high speed clock signal, wherein the pulse width of the enable signal is selected based upon the value of the pulse width selection signal. A method of testing for faults in a programmable logic device is also disclosed.