Abstract: A current source (200) comprises an input bias unit (291), a transconductance unit (295), an output bias unit (292), a combiner unit (296) and a voltage source 130'. In the transconductance unit (295), a first current mirror (215) provides currents I.sub.A and I.sub.B which are distributed to cross-coupled first and second transistors arrangements (TA 3 and TA 4). The first arrangements (TA 3) receives a control signal (V.sub.GS12) which is derived from a master signal (205') at a master terminal (205). The second arrangement (TA 4) is controlled from the first arrangement (TA 3). The transconductance ratio between the arrangements (TA 3 and TA 4) is regulated through a feedback in a second current mirror (235). A transconductance drift is substantially prevented. Output currents which are related to this stabilized transconductance ratio are provided at output terminals (203, 204). A first output current (I.sub.out1) is derived from the second arrangement (TA 3) and a second output current (I.sub.

Abstract: The amplifier (200) includes an input stage (220) coupled to two output transistors (281, 282) having a common terminal at the output terminal (206) of the amplifier. Class AB operation of the output transistors (281, 282) is possible at a comparatively low supply voltage. In order to obtain such operation, measurement transistors (271, 272) are coupled to the same control input (283, 284) as the output transistors (281, 282). These measurement transistors (271, 272) are serially coupled to a current mirror (260). The quiescent current of the output transistors (281, 282) is measured and used to produce a feedback signal which is superimposed to the control signals.

Abstract: An analog-to-digital converter is introduced which operates as an oversampled delta-sigma converter. The converter is implemented fully differentially, having doubled integrator capacitors (130, 230), comparators (180, 280), and feedback units (160, 260). In order to reduce the influence of parasitic capacities, the feedback units (160, 260) comprise cascoded switches (171-179). Internal auxiliary signals for controlling the feedback units (160, 260) return to zero at clock frequency. The converter can be used in an integrated signal processing circuit having analog and digital domains on one chip. The capacitors (130, 230) itself are implemented by MOS transistors with the same single poly process as the rest of the circuit. In a second embodiment of the invention, the analog-to-digital converter (500) comprises multiple comparators (580, 572, 573, 574), dynamic matching circuits (801, 802). The comparators (572, 573, 574) can received dithered input signals.

Abstract: A high frequency monolithic amplifier (100) is provided which can be used, for example, in the PLL prescaler of cellular radio systems. The amplifier (100) amplifies single-ended signals having a frequency in the GHz area. It includes a feedback unit (160) which uses parasitic capacitors. The feedback depends on the frequency and is positive for high frequencies and negative for low frequencies. A high gain can be obtained for high frequencies. A comparative low gain a low frequencies prevents the propagation of noise. The amplifier (100) of the present invention can be cascaded to an, for example, 3 stage amplifier arrangement (300).

Abstract: A differential-to-single-ended converter comprising a resistor network (205) and an operational amplifier is introduced. In comparison to prior art converters, a resistor (250) placed between the non-inverting input (264) of the operational amplifier (260) and the negative input terminal (202) of the converter (200). The common mode voltage (V.sub.nii ') at the non-inverting input (264) does not depend on the differential input voltage (V.sub.in.sup.#) of the converter (200) and has low fluctuations. This allows the use of an operational amplifier (260) with low CMRR and makes the converter (200) suitable for low voltage applications.

Abstract: The present invention describes a bias generator (10) which supplies a temperature stabilizing bias current (72) to a main circuit (90). The bias generator (10) comprises a measurement unit (20) having a similar structure and temperature characteristic as the main circuit (90). Measurement unit (20) supplies a temperature dependent measurement signal (27). A temperature invariant element (40) supplies a temperature independent reference signal (47). These signals (27, 47) are compared in a differential amplifier (30) which controls variable current sources (50, 60, 70). The variable current sources (50, 60) supply the measurement unit (20), the temperature invariant element (40) and the bias current (72) for the main circuit (90) itself. A negative feedback is produced which results in a stabilized transconductance of the main circuit (90). Therefore, the bias current (72) which determines all other currents and the speed of the main circuit (90) is automatically adjusted to the needs.

Abstract: An apparatus and method for performing adaptive power regulation for an integrated circuit. The present invention utilizes a voltage regulator circuit (16) to regulate the voltage provided to an integrated circuit core (12), and to thereby reduce the power consumption of the integrated circuit core (12). In one form, the voltage regulator circuit (16) utilizes two voltage converting mechanisms, namely an inductive converter (22) and a resistive converter (24). The inductive converter (22) and the resistive converter (24) supplement each other in order to supply the current required by integrated circuit core (12). All or a portion of voltage regulator (16) may be located on the same integrated circuit substrate as integrated circuit core (12).

Abstract: A switched capacitor differential circuit switches first and second differential input signals (Vinp1, Vinp2) to respective inputs (A, B) of an operational amplifier (12) via respective first and second signal paths. Each signal path includes a coupling capacitor (13, 14) and two switching devices (2, 3 and 4, 5) to switch the input signals to charge the capacitors at a first phase of a clock signal and to discharge the capacitors onto the inputs of the amplifier at a second phase of the clock signal. In order to remove common mode spikes from transferring to the amplifier, a pair of comon mode capacitors (16, 17) are coupled between the inputs and a common node (15), which is coupled via a pair of switches (6, 7) to the first and second signal paths between the capacitors and the second of the switching devices so that the coupling capacitors are discharged relative to the common node.

Abstract: A driver circuit (8) is arranged to switch a transistor (10) of a switched capacitor circuit, or transistors (62 and 64) of a differential switched capacitor circuit, between a first state, in which the transistor switch is closed whereby an input signal (VINP) is transferred to an output, and a second state, in which the transistor switch is open. The driver circuit includes a maximum and a minimum selection (12, 14) between the input signal and a reference voltage (VAG) , a voltage shift element (26), and switches (16, 18, 20, 22, 24), coupled to receive the input signal (VINP) and to the gate electrode of the transistor switch (10), which ensures that the gate-to-source voltage of the transistor switch (10), in the first and second states, is independent of the input signal (VINP).