Patents by Inventor Itamar Kazachinsky
Itamar Kazachinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10656697Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.Type: GrantFiled: March 5, 2018Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
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Publication number: 20190050041Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.Type: ApplicationFiled: March 5, 2018Publication date: February 14, 2019Inventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
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Patent number: 9910475Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.Type: GrantFiled: December 23, 2014Date of Patent: March 6, 2018Assignee: Intel CorporationInventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
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Patent number: 9696997Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.Type: GrantFiled: January 11, 2016Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
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Patent number: 9612938Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.Type: GrantFiled: May 16, 2013Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Frank Binns, Matthew C. Merten, Mayank Bomb, Beeman C. Strong, Peter Lachner, Jason W. Brandt, Itamar Kazachinsky, Ofer Levy, Md A. Rahman
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Publication number: 20160179166Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: TSVIKA KURTS, BEEMAN C. STRONG, RICHARD B. O'CONNOR, MICHAEL W. CHYNOWETH, RAJSHREE A. CHABUKSWAR, AVNER LOTTEM, ITAMAR KAZACHINSKY, MICHAEL MISHAELI, ANTHONY WOJCIECHOWSKI, VIKAS R. VASISHT
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Publication number: 20160117171Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.Type: ApplicationFiled: January 11, 2016Publication date: April 28, 2016Applicant: INTEL CORPORATIONInventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
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Patent number: 9262163Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.Type: GrantFiled: December 29, 2012Date of Patent: February 16, 2016Assignee: Intel CorporationInventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
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Patent number: 9189360Abstract: A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.Type: GrantFiled: June 15, 2013Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Beeman C. Strong, Jason W. Brandt, Tsvika Kurts, Peter Lachner, Itamar Kazachinsky, Stephen J. Robinson, Peggy J. Irelan
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Patent number: 9063729Abstract: Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.Type: GrantFiled: August 22, 2012Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Alon Naveh, Eliezer Weissmann, Itamar Kazachinsky, Iris Sorani, Yair Kazarinov
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Publication number: 20140372987Abstract: A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.Type: ApplicationFiled: June 15, 2013Publication date: December 18, 2014Inventors: Beeman C. Strong, Jason W. Brandt, Tsvika Kurts, Peter Lachner, Itamar Kazachinsky, Stephen J. Robinson, Peggy J. Irelan
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Publication number: 20140344552Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.Type: ApplicationFiled: May 16, 2013Publication date: November 20, 2014Inventors: Frank Binns, Matthew C. Merten, Mayank Bomb, Beeman C. Strong, Peter Lachner, Jason W. Brandt, Itamar Kazachinsky, Ofer Levy, MD A. Rahman
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Publication number: 20140189314Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.Type: ApplicationFiled: December 29, 2012Publication date: July 3, 2014Inventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
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Publication number: 20130036317Abstract: Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.Type: ApplicationFiled: August 22, 2012Publication date: February 7, 2013Inventors: Alon Naveh, Eliezer Weissmann, Itamar Kazachinsky, Iris Sorani, Yair Kazarinov
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Patent number: 8281083Abstract: Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.Type: GrantFiled: June 30, 2005Date of Patent: October 2, 2012Assignee: Intel CorporationInventors: Alon Naveh, Eliezer Weissmann, Itamar Kazachinsky, Iris Sorani, Yair Kazarinov
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Publication number: 20070005910Abstract: Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Alon Naveh, Eliezer Weissmann, Itamar Kazachinsky, Iris Sorani, Yair Kazarinov
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Publication number: 20060129860Abstract: A clock frequency control unit for an integrated circuit (IC) includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at least first and second states corresponding to non-low workload low workload states, respectively. In the first state, the GC provides a clock signal to functional units of the IC with the same frequency as the clock generator output. In the second state, the GC reduces the frequency of the clock signal. In one embodiment, the GC masks out selected cycles of the clock generator output to reduce the clock signal frequency. The FSM monitors the operation of the IC to transition from the first state to the second state when selected “low workload” conditions are detected (e.g., long latency cache miss). Similarly, the FSM transitions from the second state to the first state when selected “non-low workload” conditions are detected.Type: ApplicationFiled: January 12, 2006Publication date: June 15, 2006Inventors: Itamar Kazachinsky, Doron Orenstein
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Patent number: 5379396Abstract: An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.Type: GrantFiled: October 11, 1991Date of Patent: January 3, 1995Assignee: Intel CorporationInventors: Simcha Gochman, Itamar Kazachinsky, Michael Kagan
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Patent number: 5301298Abstract: An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.Type: GrantFiled: October 11, 1991Date of Patent: April 5, 1994Assignee: Intel CorporationInventors: Michael Kagan, Itamar Kazachinsky, Simcha Gochman, Tal Gat