Patents by Inventor ITAMAR RABENSTEIN
ITAMAR RABENSTEIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359537Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.Type: ApplicationFiled: July 6, 2023Publication date: November 9, 2023Inventors: Ran Koren, Shay Aisman, Itamar Rabenstein, Amir Ancel
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Patent number: 11740985Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.Type: GrantFiled: April 27, 2021Date of Patent: August 29, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Koren, Shay Aisman, Itamar Rabenstein, Amir Ancel
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Patent number: 11656958Abstract: Methods, systems, and devices for redundant data bus inversion (DBI) sharing are described. A device may identify a group of channels included in a data bus. The device may determine whether the group of channels satisfies a criterion. Based on the determination, the device may allocate an overhead channel to the group of channels for a set of redundancy operations. Based on the determination, the device may allocate the overhead channel to the group of channels for a set of data bus inversion operations. The device may encode data associated with the group of channels based on the allocation of the overhead channel. The overhead channel may be included in the data bus.Type: GrantFiled: April 29, 2021Date of Patent: May 23, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Liron Mula, Gil Levy, Itamar Rabenstein
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Publication number: 20220350713Abstract: Methods, systems, and devices for redundant data bus inversion (DBI) sharing are described. A device may identify a group of channels included in a data bus. The device may determine whether the group of channels satisfies a criterion. Based on the determination, the device may allocate an overhead channel to the group of channels for a set of redundancy operations. Based on the determination, the device may allocate the overhead channel to the group of channels for a set of data bus inversion operations. The device may encode data associated with the group of channels based on the allocation of the overhead channel. The overhead channel may be included in the data bus.Type: ApplicationFiled: April 29, 2021Publication date: November 3, 2022Inventors: Liron Mula, Gil Levy, Itamar Rabenstein
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Publication number: 20220334939Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.Type: ApplicationFiled: April 27, 2021Publication date: October 20, 2022Inventors: Ran Koren, Shay Aisman, Itamar Rabenstein, Amir Ancel
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Patent number: 11252027Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.Type: GrantFiled: January 23, 2020Date of Patent: February 15, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ortal Ben-Moshe, Lion Levi, Itamar Rabenstein, Idan Matari, Noam Michaelis, Ofir Merdler, Evyatar Romlet
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Publication number: 20210234753Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.Type: ApplicationFiled: January 23, 2020Publication date: July 29, 2021Inventors: Ortal Ben-Moshe, Lion Levi, Itamar Rabenstein, Idan Matari, Noam Michaelis, Ofir Merdler, Evyatar Romlet
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Patent number: 10708219Abstract: A method for communication, includes routing unicast data packets among nodes in a network using respective Layer-3 addresses that are uniquely assigned to each of the nodes. Respective Layer-2 unicast addresses are assigned to the nodes in accordance with an algorithmic mapping of the respective Layer-3 addresses. The unicast data packets are forwarded within subnets of the network using the assigned Layer-2 addresses.Type: GrantFiled: November 20, 2016Date of Patent: July 7, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Zachy Haramaty, Diego Crupnicoff, Freddy Gabbay, Benny Koren, Amiad Marelli, Itamar Rabenstein, Ido Bukspan, Oded Zemer
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Patent number: 10623296Abstract: A method for packet generation includes designating a group of one or more ports, from among multiple ports of one or more network elements, to perform the packet generation. A circular packet path, which traverses one or more buffers of the ports in the group, is configured. A burst of one or more packets is provided to the group, so as to cause the burst of packets to repeatedly traverse the circular packet path. A packet stream, including the repeated burst of packets, is transmitted from one of the ports.Type: GrantFiled: July 4, 2017Date of Patent: April 14, 2020Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Zachy Haramaty, Liron Mula, George Elias, Aviv Kfir, Barak Gafni, Gil Levy, Benny Koren, Itamar Rabenstein, Maty Golovaty
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Patent number: 10614181Abstract: A method for circuit design automation includes appending a non-synthesizable input having a unique identifier to HDL code that specifies a physical input of the circuit. For the physical components in the circuit to which a signal from the physical input is to propagate, corresponding non-synthesizable components are appended, having respective identifiers assigned responsively to the unique identifier of the non-synthesizable input, to the HDL code that specifies the physical components. The design is verified by simulating operation of the circuit using the HDL code, including both the physical and non-synthesizable inputs and components. After verifying the design, a netlist synthesis tool automatically generates a netlist of the circuit including the physical inputs and components while omitting the non-synthesizable inputs and components.Type: GrantFiled: February 8, 2018Date of Patent: April 7, 2020Assignee: Mellanox Technologies, Ltd.Inventors: Moshe Noah, Itamar Rabenstein, Irit Granovsky
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Patent number: 10601714Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.Type: GrantFiled: April 26, 2018Date of Patent: March 24, 2020Assignee: Mellanox Technologies TLV Ltd.Inventors: Eyal Srebro, Sagi Kuks, Liron Mula, Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Niv Aibester
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Patent number: 10419329Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.Type: GrantFiled: March 30, 2017Date of Patent: September 17, 2019Assignee: Mellanox Technologies TLV Ltd.Inventors: Lion Levi, George Elias, Oded Wertheim, Amiad Marelli, Miriam Menes, Itamar Rabenstein, Noam Avital, Evyatar Romlet, Ofir Merdler
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Publication number: 20190243936Abstract: A method for circuit design automation includes appending a non-synthesizable input having a unique identifier to HDL code that specifies a physical input of the circuit. For the physical components in the circuit to which a signal from the physical input is to propagate, corresponding non-synthesizable components are appended, having respective identifiers assigned responsively to the unique identifier of the non-synthesizable input, to the HDL code that specifies the physical components. The design is verified by simulating operation of the circuit using the HDL code, including both the physical and non-synthesizable inputs and components. After verifying the design, a netlist synthesis tool automatically generates a netlist of the circuit including the physical inputs and components while omitting the non-synthesizable inputs and components.Type: ApplicationFiled: February 8, 2018Publication date: August 8, 2019Inventors: Moshe Noah, Itamar Rabenstein, Irit Granovsky
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Patent number: 10284465Abstract: A switch includes multiple physical ports and forwarding circuitry. The physical ports are configured to receive and send packets over a network. The forwarding circuitry is configured to assign first port numbers to the physical ports, and second port numbers to temporary ports defined in addition to the physical ports, to receive a packet having a destination address via a physical port, to select, based on the destination address, an egress port number for the packet from among the first and second port numbers, to forward the packet to a physical port corresponding to the egress port number if the egress port number is one of the first port numbers, and, if the egress port number is one of the second port numbers, to map a temporary port associated with the egress port number to a mapped physical port and to forward the packet to the mapped physical port.Type: GrantFiled: December 28, 2015Date of Patent: May 7, 2019Assignee: Mellanox Technologies TLV Ltd.Inventors: Zachy Haramaty, Eitan Zahavi, Itamar Rabenstein
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Patent number: 10250530Abstract: Communication apparatus includes multiple interfaces configured to be connected to a packet data network for receiving and forwarding of data packets of multiple types. A memory is coupled to the interfaces and configured as a buffer to contain packets received through the ingress interfaces while awaiting transmission to the network via the egress interfaces. Packet processing logic is configured to maintain multiple transmit queues, which are associated with respective ones of the egress interfaces, and to place both first and second queue entries, corresponding to first and second data packets of the first and second types, respectively, in a common transmit queue for transmission through a given egress interface, while allocating respective spaces in the buffer to store the first and second data packets against separate, first and second buffer allocations, which are respectively assigned to the first and second types of the data packets.Type: GrantFiled: March 8, 2016Date of Patent: April 2, 2019Assignee: Mellanox Technologies TLV Ltd.Inventors: Niv Aibester, Amir Roitshtein, Barak Gafni, George Elias, Itamar Rabenstein
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Patent number: 10153962Abstract: Communication apparatus includes multiple interfaces connected to a packet data network, and a memory coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a test packet through an ingress interface of the apparatus, to allocate a space in the buffer for storage of a single copy of the test packet, to replicate and transmit sequentially multiple copies of the stored copy of the test packet through a designated egress interface, to receive an indication of a number of copies of the test packet that are to be transmitted, and responsively to the indication, to terminate replication of the test packet and release the allocated space in the buffer.Type: GrantFiled: June 20, 2016Date of Patent: December 11, 2018Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Amiad Marelli, George Elias, Itamar Rabenstein, Miriam Menes, Ido Bukspan
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Publication number: 20180287928Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Inventors: Lion Levi, George Elias, Oded Wertheim, Amiad Marelli, Miriam Menes, Itamar Rabenstein, Noam Avital, Evyatar Romlet, Ofir Merdler
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Publication number: 20180241677Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.Type: ApplicationFiled: April 26, 2018Publication date: August 23, 2018Inventors: Eyal Srebro, Sagi Kuks, Liron Mula, Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Niv Aibester
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Publication number: 20180152372Abstract: A method for packet generation includes designating a group of one or more ports, from among multiple ports of one or more network elements, to perform the packet generation. A circular packet path, which traverses one or more buffers of the ports in the group, is configured. A burst of one or more packets is provided to the group, so as to cause the burst of packets to repeatedly traverse the circular packet path. A packet stream, including the repeated burst of packets, is transmitted from one of the ports.Type: ApplicationFiled: July 4, 2017Publication date: May 31, 2018Inventors: Zachy Haramaty, Liron Mula, George Elias, Aviv Kfir, Barak Gafni, Gil Levy, Benny Koren, Itamar Rabenstein, Maty Golovaty
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Patent number: 9985910Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is zero are assigned to a first group, while the flows for which the respective number is non-zero are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.Type: GrantFiled: June 28, 2016Date of Patent: May 29, 2018Assignee: Mellanox Technologies TLV Ltd.Inventors: Barak Gafni, Benny Koren, George Elias, Itamar Rabenstein, Eyal Srebro, Sagi Kuks, Niv Aibester