Patents by Inventor Itsuko Sakai

Itsuko Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672615
    Abstract: A plasma processing, apparatus of an embodiment includes a chamber, an introducing part, a first power source, a holder, an electrode, and a second power source. The introducing part introduces gas into the chamber. The first power source outputs a first voltage for generating ions from the gas. The holder holds a substrate. The electrode is opposite to the ions across the substrate, and has a surface not parallel to the substrate. The second power source applies a second voltage to the electrode. The second voltage has a frequency lower than the frequency of the first voltage and Introduces die ions to the substrate.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yosuke Sato, Akio Ui, Itsuko Sakai
  • Patent number: 10026622
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsuhiro Omura, Tsubasa Imamura, Itsuko Sakai
  • Publication number: 20180012768
    Abstract: A plasma processing, apparatus of an embodiment includes a chamber, an introducing part, a first power source, a holder, an electrode, and a second power source. The introducing pat introduces gas into the chamber. The first power source outputs a first voltage for generating ions from the gas. The holder holds a substrate. The electrode is opposite to the ions across the substrate, and has a surface not parallel to the substrate. The second power source applies a second voltage to the electrode. The second voltage has a frequency lower than the frequency of the first voltage and Introduces die ions to the substrate.
    Type: Application
    Filed: February 23, 2017
    Publication date: January 11, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke SATO, Akio Ul, Itsuko Sakai
  • Publication number: 20170271170
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 21, 2017
    Inventors: Mitsuhiro OMURA, Tsubasa IMAMURA, Itsuko SAKAI
  • Patent number: 8580652
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
  • Patent number: 8339615
    Abstract: An edge detection method includes preparing a transparent substrate which includes a first main face having a first main region and a first peripheral region and a second main face having a second main region and a second peripheral region, the first peripheral region having an inclination angle of ?a1 and the second peripheral region having an inclination angle of ?a2, causing measuring light to enter the first peripheral region from a direction perpendicular to the first main region, detecting a non-emitting region where the measuring light is not emitted from the second peripheral region, and detecting an edge of the transparent substrate on the basis of the non-emitting region, wherein if a refractive index of the transparent substrate is n, the inclination angles ?a1 and ?a2satisfy the following expression: n×sin(?a1+?a2?arcsin(sin ?a1/n))?1.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohi, Itsuko Sakai, Takayuki Sakai, Shunji Kikuchi, Takuto Inoue, Akihiro Hori, Masayuki Narita
  • Publication number: 20120315758
    Abstract: According to one embodiment, a semiconductor device manufacturing method comprises mounting a supporting substrate on a front surface side of a silicon substrate having an interconnection layer and function elements formed on a front surface side, polishing a back surface side of the silicon substrate, forming a mask having an opening and an opening for a dummy hole having a diameter smaller than that of the above opening on the back surface side of the silicon substrate, etching portions exposed to the openings of the mask from the back surface side of the silicon substrate to form a via hole that reaches a part of the interconnection layer and form a dummy hole to an intermediate portion of the silicon substrate, and forming an interconnection material in the via hole.
    Type: Application
    Filed: March 21, 2012
    Publication date: December 13, 2012
    Inventors: Noriko SAKURAI, Mitsuhiro Omura, Toshiyuki Sasaki, Itsuko Sakai
  • Publication number: 20110068476
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 24, 2011
    Inventors: Atsuko KAWASAKI, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
  • Patent number: 7767055
    Abstract: A capacitive coupling plasma processing apparatus includes a process chamber configured to have a vacuum atmosphere, and a process gas supply section configured to supply a process gas into the chamber. In the chamber, a first electrode and a second electrode are disposed opposite each other. An RF power supply is disposed to supply an RF power to the first or second electrode to form an RF electric field within a plasma generation region between the first and second electrodes, so as to turn the process gas into plasma. The target substrate is supported by a support member between the first and second electrodes such that a process target surface thereof faces the second electrode. A conductive functional surface is disposed in a surrounding region around the plasma generation region and grounded to be coupled with the plasma in a sense of DC to expand the plasma.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: August 3, 2010
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Shinji Himori, Noriaki Imai, Katsumi Horiguchi, Takaaki Nezu, Shoichiro Matsuyama, Hiroki Matsumaru, Toshihiro Hayami, Kazuya Nagaseki, Itsuko Sakai, Tokuhisa Ohiwa, Yoshikazu Sugiyasu
  • Publication number: 20100027032
    Abstract: An edge detection method includes preparing a transparent substrate which includes a first main face having a first main region and a first peripheral region and a second main face having a second main region and a second peripheral region, the first peripheral region having an inclination angle of ?a1 and the second peripheral region having an inclination angle of ?a2, causing measuring light to enter the first peripheral region from a direction perpendicular to the first main region, detecting a non-emitting region where the measuring light is not emitted from the second peripheral region, and detecting an edge of the transparent substrate on the basis of the non-emitting region, wherein if a refractive index of the transparent substrate is n, the inclination angles ?a1 and ?a2 satisfy the following expression: n×sin(?a1+?a2?arcsin(sin ?a1/n))?1
    Type: Application
    Filed: July 28, 2009
    Publication date: February 4, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Dohi, Itsuko Sakai, Takayuki Sakai, Shunji Kikuchi, Takuto Inoue, Akihiro Hori, Masayuki Narita
  • Patent number: 7628931
    Abstract: In order to facilitate control of a circulating gas, in a processing apparatus 100 having a showerhead 200 for supplying a processing gas into a processing chamber via a plurality of gas supply holes, a turbo pump 120 for evacuating the processing gas from the processing chamber 110 and a circulating gas piping 150 for returning at least a portion (circulating gas Q2) of the exhaust gas evacuated from the processing chamber by the turbo pump to the showerhead, the showerhead is provided with a primary gas supply system that supplies a primary gas Q1 supplied from a gas source 140 into the processing chamber via a plurality of primary gas outlet holes h1 and a circulating gas supply system that supplies the circulating gas into the processing chamber via a plurality of circulating gas supply holes h2, with the primary gas supply system and the circulating gas supply system constituted as systems independent of each other.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: December 8, 2009
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Masashi Saito, Yusuke Hirayama, Itsuko Sakai, Tokuhisa Ohiwa
  • Patent number: 7368876
    Abstract: A low-cost plasma processing apparatus which permits reduction of the cost, as well as reduction of the loss of transmitted power. The plasma processing apparatus 1 has an apparatus main body 2 and auxiliary equipment 3. The auxiliary equipment 3 is comprised of a power supply apparatus 5 that supplies power to a processing chamber 4, and a plurality of dry pumps 6 and 7, and so on. The power supply apparatus 5 is comprised of a matching unit 9, an RF amplifier 13 that is connected to the matching unit 9 via a coaxial cable 24, and a power controller 12 having a DC amplifier 14 therein. The RF amplifier 13 is formed in a separate body to the DC amplifier 14 and disposed in a position away from the DC amplifier 14 and close to the matching unit 9, and is connected to the DC amplifier 14 via an ordinary cable 25.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: May 6, 2008
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Toshihiro Hayami, Etsuji Ito, Itsuko Sakai
  • Publication number: 20070227033
    Abstract: A substrate transferring apparatus capable of suppressing particles from being produced. The substrate processing apparatus (1) includes a processing chamber (12) in which a wafer (W) is housed, a transfer arm (17) for transferring the wafer to the processing chamber, and a susceptor (45) which is disposed in the processing chamber and on which the transferred wafer is mounted. An electrostatic chuck (55) having a plurality of protrusions (55a) is disposed In an upper portion of the susceptor. A transfer fork (25) having a plurality of protrusions (25a) for holding a wafer is disposed on a distal end of the transfer arm. These protrusions (25a) are provided in the transfer fork (25) such that wafer holding portions (81) by the protrusions (25a) are different from wafer holding protrusions (80) by the protrusions (55a) of the electrostatic chuck.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 4, 2007
    Applicants: TOKYO ELECTRON LIMITED, Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Kobayashi, Itsuko Sakai, Tokuhisa Ohiwa
  • Patent number: 7186315
    Abstract: There is provided a plasma treatment apparatus that carries out plasma treatment on an article, with which it is possible to make the plasma density uniform. A plasma treatment vessel houses a semiconductor wafer and a treatment gas is introduced into the plasma treatment vessel. A lower electrode is provided inside the plasma treatment vessel and the semiconductor wafer is placed onto the lower electrode. An upper electrode that has a plurality of holes formed therein and has a dome shape that is upwardly convex, is provided above the lower electrode in the plasma treatment vessel. A height of the upper electrode from the lower electrode becomes greater from an outside of the lower electrode to a center of the lower electrode.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: March 6, 2007
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Shinji Himori, Itsuko Sakai
  • Patent number: 7182879
    Abstract: A plasma processing method, in which a process gas is introduced into an evacuated process chamber for subjecting the target object to a plasma processing. The plasma processing method is featured in that at least a part of the process gas exhausted from the process chamber is introduced again into the process chamber. A specified value is obtained by monitoring the state of the plasma of the process gas within the process chamber, and the introducing conditions of the process gas into the process chamber are controlled to adjust a predetermined property value to a regulated value.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: February 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Itsuko Sakai, Tokuhisa Ohiwa
  • Publication number: 20060231877
    Abstract: A semiconductor device comprises a semiconductor substrate having a surface of a plane orientation {100}, and a plurality of memory cells formed on the semiconductor substrate. The memory cells each include a capacitor formed in a trench extending from the surface into the semiconductor substrate, and a transistor. The transistor has a first source/drain region connected to the capacitor, a second source/drain region formed apart from the first source/drain region as leaving an interval therebetween and connected to a bit line, and a gate electrode formed over the interval between the first and second source/drain regions and connected to a word line. A transverse section of at least part of the trench is tetragonal. Transverse sections of the trenches in the memory cells are tilted at the substantially same angle against a direction of extension of the word line.
    Type: Application
    Filed: June 17, 2005
    Publication date: October 19, 2006
    Inventors: Keiichi Takenaka, Katsunori Yahashi, Itsuko Sakai
  • Publication number: 20060137988
    Abstract: According to an aspect of the present invention, a semiconductor manufacturing apparatus, including: a treatment chamber configured to house a substrate; an electrode which is disposed in said treatment chamber and on which the substrate is placed; a robot arm configured to convey the substrate to said electrode; and a sensor configured to detect a detection pattern of a focus ring which is disposed on an outer peripheral edge portion of said electrode, surrounds an peripheral edge of the substrate placed on said electrode and has the detection pattern, wherein clearance between the substrate and the focus ring is adjusted based on detection result of said sensor, is provided.
    Type: Application
    Filed: March 16, 2005
    Publication date: June 29, 2006
    Inventors: Katsunori Yahashi, Keiichi Takenaka, Masaki Narita, Itsuko Sakai
  • Publication number: 20060128093
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises forming a mask member on a surface of a semiconductor substrate; and forming a trench in the semiconductor substrate by selectively etching the semiconductor substrate with a mask of the mask member under a certain pressure. The pressure is changed on arrival of (Etching Depth)/(Aperture Width in said surface) at 30 or more for the remainder of the etching by a factor ranging from 1/2 to 9/10 relative to the pressure at the time of the arrival.
    Type: Application
    Filed: April 14, 2005
    Publication date: June 15, 2006
    Inventors: Keiichi Takenaka, Katsunori Yahashi, Itsuko Sakai, Masaki Narita
  • Publication number: 20060118044
    Abstract: A capacitive coupling plasma processing apparatus includes a process chamber configured to have a vacuum atmosphere, and a process gas supply section configured to supply a process gas into the chamber. In the chamber, a first electrode and a second electrode are disposed opposite each other. An RF power supply is disposed to supply an RF power to the first or second electrode to form an RF electric field within a plasma generation region between the first and second electrodes, so as to turn the process gas into plasma. The target substrate is supported by a support member between the first and second electrodes such that a process target surface thereof faces the second electrode. A conductive functional surface is disposed in a surrounding region around the plasma generation region and grounded to be coupled with the plasma in a sense of DC to expand the plasma.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 8, 2006
    Inventors: Shinji Himori, Noriaki Imai, Katsumi Horiguchi, Takaaki Nezu, Shoichiro Matsuyama, Hiroki Matsumaru, Toshihiro Hayami, Kazuya Nagaseki, Itsuko Sakai, Tokuhisa Ohiwa, Yoshikazu Sugiyasu
  • Patent number: 7022616
    Abstract: This invention provides the following high-rate silicon etching method. An object to be processed W having a silicon region is so set as to be in contact with a process space in a process chamber that can be held in vacuum. An etching gas is introduced into the process space to form a gas atmosphere at a gas pressure of 13 Pa to 1,333 Pa (100 mTorr to 10 Torr). A plasma is generated upon application of RF power. In the plasma, the sum of the number of charged particles such as ions and the number of radicals increases, and etching of the silicon region is performed at a higher rate than in conventional etching.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: April 4, 2006
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Takanori Mimura, Kazuya Nagaseki, Itsuko Sakai, Tokuhisa Ohiwa