Abstract: In a method for testing a counter, the counter is first set at a predetermined initial value. Then, the counter is incremented in response to the clocks. The number of the clocks is counted until a carry is outputted from the counter to provide an actual counted value. The actual counted value is compared to a reference value, which is calculated in advance. And then, the counter is decided whether to be operating normally or not on the basis of the result of the comparison.

Abstract: A method and apparatus for performing a specified test on a semiconductor memory device having a clock generating circuit and a control circuit in which the clock generating circuit generates a clock signal in response to an operation request signal and the control circuit generates a reset signal for stopping generation of the clock signal after a predetermined period of time. The control circuit also generates at least one operation control signal for performing a fundamental operation of the memory device in response to the clock signal. The test is performed by inputting a test mode signal to the semiconductor memory device to initiate the specified test, delaying generation of the reset signal for a period of time exceeding the predetermined period of time, carrying out the specified test while the test mode signal is being input, and terminating the specified test by stopping input of the test mode signal.

Abstract: According to one aspect of the invention, a serial access memory has multiple shift registers that are clocked simultaneously for designating column addresses. Each shift register shifts an enabling signal that enables access to a certain number of bits at a time. By operating together, the shift registers enable simultaneous access to a multiple of that number of bits. This multiple can be varied to design serial access memories with different word widths. According to another aspect of the invention, there need be only one shift register, but its stages are interleaved. The enabling signal is shifted from a first end of the shift register to a second end, skipping every other stage, then shifted back from the second end to the first end through the stages that were skipped. This operation is repeated cyclically.

Abstract: A semiconductor memory device has memory cells in which data are represented by a first voltage level and a second voltage level higher than the first voltage level. The memory cells are selected by word lines. When memory cells are not selected, the word lines are driven to a third voltage level lower than the first voltage level.

Abstract: A serial access memory includes a pair of bit lines, a plurality of memory cells each coupled to one of the bit lines and a pair of data lines. The serial access memory also includes a sense amplifier drive line, a sense amplifier, data latch circuit, data transfer circuit and a drive capability control circuit. The sense amplifier drive line is coupled to a potential source for supplying a sense amplifier drive signal from the potential source. The sense amplifier is coupled to the bit lines and the sense amplifier drive line for amplifying a difference of electrical potentials appeared on the bit lines in response to the sense amplifier drive signal. The data latch circuit is coupled to the bit lines and the data lines for latching the amplified electrical potentials appeared on the bit lines as data. The data transfer circuit is coupled between the bit lines and the data latch circuit for controlling an electrical connection between the bit lines and the data latch circuit.

Abstract: A self-refreshing memory has a refresh timer that generates refresh requests at a certain rate, and a refresh address counter that generates refresh addresses by counting the refresh requests. A refresh test circuit receives test signals from automatic test equipment that cause it to disable the refresh timer, reset the refresh address counter, then enable the refresh timer for a certain interval. At the end of this interval the refresh test circuit disables the refresh timer again and generates an output signal such as a serial data signal indicating the current refresh address, or a pass-fail signal indicating whether the refresh address is equal to or greater than a preset pass value.