Abstract: One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, an oscillator comprises a voltage controlled oscillator configured to generate an output clock based on a drive signal, a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, and an integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage.

Abstract: One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, an oscillator comprises a voltage controlled oscillator configured to generate an output clock based on a drive signal, a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, and an integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage.

Abstract: A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.

Abstract: Systems, methods, and devices for providing power to low energy circuits include inrush circuits. Devices include a regulator that includes at least one driver device configured to generate a first current associated with a load comprising a low energy integrated circuit. Devices also include a bias generator configured to generate a second current to charge a load capacitor coupled with a power terminal of the low energy integrated circuit. Devices further include an enable circuit configured to enable the bias generator and disable the regulator responsive to a load voltage being below a threshold voltage, and further configured to enable the regulator to generate the first current and disable the bias generator responsive to the load voltage being above the threshold voltage.

Abstract: A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.

Abstract: A method of biasing a circuit includes generating a control bias signal based on a difference between a leakage current of a baseline circuit and a reference signal; applying the control bias signal to a charge pump circuit to set a value of a reverse body bias voltage output from the charge pump, the control bias signal providing analog control of a digital clock of the charge pump circuit; and applying the reverse body bias voltage to a body of the baseline circuit.

Abstract: A substrate bias circuit may measure a leakage current of a baseline device, compare the leakage current with a reference current, and based on the comparison, adjust a reverse body bias voltage applied to a body of the baseline device.

Abstract: Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.

Abstract: Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.

Abstract: A shunt type voltage regulator circuit (300) can include a load supply circuit (306) and feedback circuit (308-0) that provide impedance modulated according to a first feedback circuit (308), thus limiting power consumption at higher power supply ranges. In addition, a faster regulation response can be provided by a current conveyor circuit (312?) that can force the voltage at a regulated load node (304) to match that at a replication node (316).

Abstract: Bandgap reference (BGR) circuits and methods are described herein for providing high accuracy, low power Bandgap operation when using small, low voltage devices in the analog blocks of the BGR circuit. In some cases, chopped input stabilization and dynamic current matching techniques may be combined to compensate for input voltage offsets in the operational amplifier portion and current offsets in the current mirror portion of the Bandgap circuit. When used together, the chopped stabilization and dynamic current matching techniques provide a significant increase in accuracy, especially when using small, low voltage devices in the analog blocks to reduce layout area and support low power supply operation (e.g., power supply values down to about 1.4 volts and below).

Abstract: An apparatus comprising a first bus, a second bus, a memory and one or more interconnections. The memory may be connected to the first bus and the second bus and may be configured to transfer data over the first bus and the second bus. The one or more interconnections may be connected between one or more data lines of the first bus and the second bus to control a bit-width of the first and second buses.

Abstract: A method and apparatus for sensing the state of a memory cell and equalizing bit line voltages without using ATD circuitry. One embodiment of the present invention is a memory device that includes a memory cell coupled to a pair of bit lines, a bit line load circuit coupled to the bit lines, an equalization circuit coupled to the bit lines, and a sense amplifier circuit having inputs coupled to the bit lines and an output coupled to the equalization circuit. The memory cell may be an SRAM cell with a pair of cross-coupled inverters. The equalization circuit may be an SRAM cell with a pair of inverters that are not cross coupled. The inputs of the inverters in the equalization circuit may receive signals output by the sense amplifier circuit, and the outputs of the inverters may be coupled to the pair of bit lines. The sense amplifier senses data output by the memory cell to the bit lines, and generates output signals.