Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

Abstract: A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.

Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.

Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.

Abstract: A package comprising at least one electronic chip, a first heat removal body thermally coupled to a first main surface of the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and part of the first heat removal body, wherein at least part of a surface of the first heat removal body is roughened.

Abstract: A package comprising at least one electronic chip, a first heat removal body thermally coupled to a first main surface of the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and part of the first heat removal body, wherein at least part of a surface of the first heat removal body is roughened.

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.

Abstract: A package comprising at least one electronic chip, a first heat removal body thermally coupled to a first main surface of the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and part of the first heat removal body, wherein at least part of a surface of the first heat removal body is roughened.

Abstract: A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.

Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.

Abstract: According to an exemplary aspect an electronic module is provided, wherein the electronic module comprises an electronic chip comprising at least one electronic component, a spacing element comprising a main surface arranged on the electronic chip and being in thermally conductive connection with the at least one electronic component, and a mold compound at least partially enclosing the electronic chip and the spacing element, wherein the spacing element comprises a lateral surface which is in contact to the mould compound and comprises surface structures.

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

Abstract: According to an exemplary aspect an electronic module is provided, wherein the electronic module comprises an electronic chip comprising at least one electronic component, a spacing element comprising a main surface arranged on the electronic chip and being in thermally conductive connection with the at least one electronic component, and a mold compound at least partially enclosing the electronic chip and the spacing element, wherein the spacing element comprises a lateral surface which is in contact to the mould compound and comprises surface structures.

Abstract: A semiconductor device includes a first chip coupled to an electrical insulator, and a sintered heat conducting layer disposed between the electrical insulator and the first chip.

Abstract: According to an exemplary aspect an electronic module is provided, wherein the electronic module comprises an electronic chip comprising at least one electronic component, a spacing element comprising a main surface arranged on the electronic chip and being in thermally conductive connection with the at least one electronic component, and a mold compound at least partially enclosing the electronic chip and the spacing element, wherein the spacing element comprises a lateral surface which is in contact to the mold compound and comprises surface structures.

Abstract: A method which comprises arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of a substrate and a wall delimited by a respective one of a plurality of holes in an electrically conductive frame arranged on the substrate, at least partially encapsulating the electronic chips in the chip accommodation cavities by an encapsulant, and forming electrically conductive contacts for electrically contacting the at least partially encapsulated electronic chips.