Abstract: The disclosed embodiments provide an apparatus for connecting one or more optical fibers to an optoelectronic system. This apparatus includes a packaged optoelectronic module (POeM) comprising an optical connector, a silicon photonic (SiP) chip, an integrated circuit (IC) chip, at least one laser chip and a package substrate. The apparatus also includes an assembly adapter enclosing the POeM, wherein the assembly adapter includes a mechanical transfer (MT) ferrule cavity, which includes one or more coarse-alignment structures to guide an MT ferrule enclosing at least one optical fiber during assembly of the apparatus. The assembly adapter is comprised of a solder-reflow-compatible material to facilitate bonding the assembly adapter to a circuit board.

Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.

Abstract: In some embodiments, an integrated photonic module contains, a silicon-on-insulator platform, an integrated photonic component, and an optical fiber. The silicon-on-insulator platform can contain a silicon-on-insulator photonic circuit, a co-fabricated spot size converter, and a co-fabricated micromachined trench structure. The co-fabricated micromachined trench structure can contain dimensions compatible with the optical fiber, and the optical fiber can be bonded to, and disposed at least partially within, the micromachined trench structure. The optical modes of the optical fiber, the integrated photonic component, the co-fabricated spot size converter, and the silicon-on-insulator photonic circuit can also be spatially aligned with one another.

Abstract: The disclosed embodiments provide an apparatus for connecting one or more optical fibers to an optoelectronic system. This apparatus includes a packaged optoelectronic module (POeM) comprising an optical connector, a silicon photonic (SiP) chip, an integrated circuit (IC) chip, at least one laser chip and a package substrate. The apparatus also includes an assembly adapter enclosing the POeM, wherein the assembly adapter includes a mechanical transfer (MT) ferrule cavity, which includes one or more coarse-alignment structures to guide an MT ferrule enclosing at least one optical fiber during assembly of the apparatus. The assembly adapter is comprised of a solder-reflow-compatible material to facilitate bonding the assembly adapter to a circuit board.

Abstract: The disclosed embodiments relate to a system that implements a hybrid laser. This system includes a reflective gain medium (RGM) comprising an optical gain material coupled to a mirror. This RGM is coupled to a spot-size converter (SSC), which optically couples the RGM to an optical reflector through a silicon waveguide. The SSC converts an optical mode-field size of the RGM to an optical mode-field size of the silicon waveguide. During operation, the RGM, the spot-size converter, the silicon waveguide and the silicon mirror collectively form a lasing cavity, wherein an effective thermo-optic coefficient (TOC) of a portion of the lasing cavity that passes through the optical gain material and the SSC material is substantially the same as the TOC of silicon. Finally, a laser output is optically coupled out of the lasing cavity.

Abstract: A multi-chip module (MCM) is described. This MCM includes a driver integrated circuit that includes electrical circuits, a photonic chip, an interposer, and an optical gain chip. The photonic chip may be implemented using a silicon-on-insulator technology, and may include an optical waveguide that conveys an optical signal and traces that are electrically coupled to the driver integrated circuit. Moreover, the interposer may be electrically coupled to the traces. Furthermore, the optical gain chip may include a III/V compound semiconductor (and, more generally, a semiconductor other than silicon), and may include a second optical waveguide that conveys the optical signal and that is vertically aligned with the optical waveguide relative to a top surface of the interposer. Additionally, the optical gain chip may be electrically coupled to the interposer.

Abstract: A hybrid optical source comprises an optical gain chip containing an optical gain material that provides an optical signal, and an optical reflector chip including an optical reflector. It also includes a semiconductor-on-insulator (SOI) chip, which comprises a semiconductor layer having a planarized surface facing the semiconductor reflector. The semiconductor layer includes: an optical coupler to redirect the optical signal to and from the planarized surface; and an optical waveguide to convey the optical signal from the optical coupler. While assembling these chips, a height of the optical gain material is referenced against the planarized surface of the semiconductor layer, a height of the optical reflector is referenced against the planarized surface of the semiconductor layer, and the optical reflector is aligned with the optical coupler, so that the optical signal emanating from the optical gain material is reflected by the optical reflector and into the optical coupler.

Abstract: A hybrid optical source comprises an optical gain chip containing an optical gain material that provides an optical signal, and an optical reflector chip including an optical reflector. It also includes a semiconductor-on-insulator (SOI) chip, which comprises a semiconductor layer having a planarized surface facing the semiconductor reflector. The semiconductor layer includes: an optical coupler to redirect the optical signal to and from the planarized surface; and an optical waveguide to convey the optical signal from the optical coupler. While assembling these chips, a height of the optical gain material is referenced against the planarized surface of the semiconductor layer, a height of the optical reflector is referenced against the planarized surface of the semiconductor layer, and the optical reflector is aligned with the optical coupler, so that the optical signal emanating from the optical gain material is reflected by the optical reflector and into the optical coupler.

Abstract: A multi-chip module (MCM) is described. This MCM includes a driver integrated circuit that includes electrical circuits, a photonic chip, an interposer, and an optical gain chip. The photonic chip may be implemented using a silicon-on-insulator technology, and may include an optical waveguide that conveys an optical signal and traces that are electrically coupled to the driver integrated circuit. Moreover, the interposer may be electrically coupled to the traces. Furthermore, the optical gain chip may include a III/V compound semiconductor (and, more generally, a semiconductor other than silicon), and may include a second optical waveguide that conveys the optical signal and that is vertically aligned with the optical waveguide relative to a top surface of the interposer. Additionally, the optical gain chip may be electrically coupled to the interposer.

Abstract: A photonic integrated circuit (PIC) is described. This PIC includes an inverse facet mirror on a silicon optical waveguide for optical proximity coupling between two silicon-on-insulator (SOI) chips placed face to face. Accurate mirror facets may be fabricated in etch pits using a silicon micro-machining technique, with wet etching of the silicon <110> facet at an angle of 45° when etched through the <100> surface. Moreover, by filling the etch pit with polycrystalline silicon or another filling material that has an index of refraction similar to silicon (such as a silicon-germanium alloy), a reflecting mirror with an accurate angle can be formed at the end of the silicon optical waveguide using: a metal coating, a dielectric coating, thermal oxidation, or selective silicon dry etching removal of one side of the etch pit to define a cavity.

Abstract: A multi-chip module (MCM) includes: an interposer, a photonic chip, an optical gain chip, and a waveguide-fiber connector. The photonic chip, which may be electrically coupled to the interposer, may be implemented using a silicon-on-insulator (SOI) technology, and may include an optical waveguide that conveys an optical signal. Moreover, the optical gain chip, which may be electrically coupled to the interposer, may include a III-V compound semiconductor, and may include a second optical waveguide that conveys the optical signal and that is vertically aligned with the optical waveguide relative to a top surface of the interposer. Furthermore, the waveguide-fiber connector may be mechanically coupled to the interposer, and remateably mechanically coupled to an optical fiber coupler that includes the optical fiber. The waveguide-fiber connector may convey the optical signal between the optical waveguide in the photonic chip and the optical fiber.

Abstract: A technique for fabricating a hybrid optical source is described. During this fabrication technique, a III-V compound-semiconductor active gain medium is integrated with a silicon-on-insulator (SOI) chip (or wafer) using edge coupling to form a co-planar hybrid optical source. Using a backside etch-assisted cleaving technique, and a temporary transparent substrate with alignment markers, a III-V compound-semiconductor chip with proper edge polish and coating can be integrated with a processed SOI chip (or wafer) with accurate alignment. This fabrication technique may significantly reduce the alignment complexity when fabricating the hybrid optical source, and may enable wafer-scale integration.

Abstract: A standard-CMOS-process-compatible optical mode converter transitions an optical mode size using a series of adjacent regions having different optical mode sizes. In particular, in a partial-slab-mode region, which is adjacent to an initial rib-optical-waveguide-mode region, a width of a slab portion of the rib-type optical waveguide decreases and a width of a rib portion of the rib-type optical waveguide decreases to a first minimum tip size. Then, in a slab-mode region, which is adjacent to the partial-slab-mode region, the width of the slab portion decreases to a second minimum tip size. In addition, a dielectric layer is disposed over the slab portion, the rib portion and the BOX layer in the partial-slab-mode region, the slab portion and the BOX layer in the slab-mode region, and the BOX layer in a released-mode region that is adjacent to the slab-mode region and that does not include the semiconductor layer.

Abstract: A standard-CMOS-process-compatible optical mode converter transitions an optical mode size using a series of adjacent regions having different optical mode sizes. In particular, in a partial-slab-mode region, which is adjacent to an initial rib-optical-waveguide-mode region, a width of a slab portion of the rib-type optical waveguide decreases and a width of a rib portion of the rib-type optical waveguide decreases to a first minimum tip size. Then, in a slab-mode region, which is adjacent to the partial-slab-mode region, the width of the slab portion decreases to a second minimum tip size. In addition, a dielectric layer is disposed over the slab portion, the rib portion and the BOX layer in the partial-slab-mode region, the slab portion and the BOX layer in the slab-mode region, and the BOX layer in a released-mode region that is adjacent to the slab-mode region and that does not include the semiconductor layer.

Abstract: A multi-chip module (MCM) is described. This MCM includes two substrates that are passively self-assembled on another substrate using hydrophilic and hydrophobic materials on facing surfaces of the substrates and liquid surface tension as the restoring force. In particular, regions with a hydrophilic material on the two substrates overlap regions with the hydrophilic material on the other substrate. These regions on the other substrate may be surrounded by a region with a hydrophobic material. In addition, spacers on a surface of at least one of the two substrates may align optical waveguides disposed on the two substrates, so that the optical waveguides are coplanar. This fabrication technique may allow low-loss hybrid optical sources to be fabricated by edge coupling the two substrates. For example, a first of the two substrates may be a III/V compound semiconductor and a second of the two substrates may be a silicon-on-insulator photonic chip.

Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.

Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.

Abstract: A multi-chip module (MCM) is described. This MCM includes two substrates that are passively self-assembled on another substrate using hydrophilic and hydrophobic materials on facing surfaces of the substrates and liquid surface tension as the restoring force. In particular, regions with a hydrophilic material on the two substrates overlap regions with the hydrophilic material on the other substrate. These regions on the other substrate may be surrounded by a region with a hydrophobic material. In addition, spacers on a surface of at least one of the two substrates may align optical waveguides disposed on the two substrates, so that the optical waveguides are coplanar. This fabrication technique may allow low-loss hybrid optical sources to be fabricated by edge coupling the two substrates. For example, a first of the two substrates may be a III/V compound semiconductor and a second of the two substrates may be a silicon-on-insulator photonic chip.

Abstract: An optical device is described. This optical device includes optical components having resonance wavelengths that match target values with a predefined accuracy (such as 0.1 nm) and with a predefined time stability (such as permanent or an infinite time stability) without thermal tuning and/or electronic tuning. The stable, accurate resonance wavelengths may be achieved using a wafer-scale, single (sub-second) shot trimming technique that permanently corrects the phase errors induced by material variations and fabrication inaccuracies in the optical components (and, more generally, resonant silicon-photonic optical components). In particular, the trimming technique may use photolithographic exposure of the optical components on the wafer in parallel, with time-modulation for each individual optical component based on active-element control.

Abstract: An optical device is described. This optical device includes optical components having resonance wavelengths that match target values with a predefined accuracy (such as 0.1 nm) and with a predefined time stability (such as permanent or an infinite time stability) without thermal tuning and/or electronic tuning. The stable, accurate resonance wavelengths may be achieved using a wafer-scale, single (sub-second) shot trimming technique that permanently corrects the phase errors induced by material variations and fabrication inaccuracies in the optical components (and, more generally, resonant silicon-photonic optical components). In particular, the trimming technique may use photolithographic exposure of the optical components on the wafer in parallel, with time-modulation for each individual optical component based on active-element control.