Patents by Inventor Ivar Wold

Ivar Wold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5724589
    Abstract: A development system providing a property-method-event programming (PME) model for developing context-free reusable software components is described. Despite the absence of any C++ language support for events, the present invention provides a type-safe "wiring" mechanism--one using standard C++ to dispatch an event, raised by one object (the "event source"), to a method of another object (the "event sink"), with the requirement that the event source does not need to know the class of the event sink. As a result, the system allows developers to create C++ software components which can be connected together without the components having to know anything about the makeup of the component to which it is connected. Thus, developers can create pre-packaged, re-usable software components which can simply be "plugged into" a design--all accomplished within the confines of the standard C++ programming language (i.e., without having to employ proprietary extensions).
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: March 3, 1998
    Assignee: Borland International, Inc.
    Inventor: Ivar Wold
  • Patent number: 3942173
    Abstract: An analog-to-digital converter of the ramp-integrator type utilizing a special technique to reduce errors due to offset voltages. In a pre-conversion cycle, the integrator first is ramped away from a datum level and then back to that level, by sequential application of opposite-polarity reference signals. A digital net offset error is thereby determined as the difference in clock time between (a) the total time of ramp-up-and-back and (b) a fixed time period set by a clock generator. During the subsequent conversion cycle, the integrator is ramped up by the unknown analog signal and then is ramped back by a reference signal. The time of ramp-up is controlled in accordance with the amount of previously-determined net offset error so as to provide error correction.In the embodiment disclosed, the ramp-up time during the pre-conversion cycle is set at k/2 clock pulses, and the digital offset error is the difference in clock pulse time between the return to datum level and a fixed time of k clock pulses.
    Type: Grant
    Filed: July 15, 1974
    Date of Patent: March 2, 1976
    Assignee: Analog Devices, Inc.
    Inventor: Ivar Wold
  • Patent number: RE29992
    Abstract: An analog-to-digital converter of the ramp-integrator type utilizing a special technique to reduce errors due to offset voltages. The integrator first is ramped up and then back to a reference level, by sequential application of opposite-polarity reference signals. A digital determination of net offset error then is made by comparing the total time of ramp-up-and-back with a fixed time period set by a clock generator. During the subsequent conversion operation, integration of the analog signal is controlled in accordance with the amount of net offset error so as to provide a feed-forward error correction. Integration is always in the same direction away from zero for analog signals of either polarity, thus avoiding the effects of discontinuity around zero input.
    Type: Grant
    Filed: March 15, 1977
    Date of Patent: May 8, 1979
    Assignee: Analog Devices, Incorporated
    Inventor: Ivar Wold