Patents by Inventor Iwen Yao
Iwen Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8890722Abstract: A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed.Type: GrantFiled: June 11, 2012Date of Patent: November 18, 2014Assignee: QUALCOMM IncorporatedInventors: Atul A. Salvekar, Young Geun Cho, Jia Tang, Shantanu Khare, Ming-Chieh Kuo, Iwen Yao
-
Patent number: 8787433Abstract: A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.Type: GrantFiled: October 30, 2008Date of Patent: July 22, 2014Assignee: Qualcomm IncorporatedInventors: Arunava Chaudhuri, Iwen Yao, Jeremy H. Lin, Remi Gurski
-
Patent number: 8738680Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.Type: GrantFiled: March 26, 2009Date of Patent: May 27, 2014Assignee: Qualcomm IncorporatedInventors: Arunava Chaudhuri, Hemanth Sampath, Iwen Yao, Jeremy H. Lin, Raghu N. Challa, Min Wu
-
Patent number: 8719658Abstract: A method for accessing extrinsic information in a turbo decoder is disclosed. Operation phases for Forward State Metric Calculators (FSMCs) and Reverse State Metric Calculators (RSMCs) in multiple maximum a posteriori probability (MAP) decoders are misaligned differently based on whether a current half iteration is even or odd. First extrinsic information is read from a memory into the FSMCs and RSMCs using the misaligned operation phases. Second extrinsic information is determined using the MAP decoders. Each row of the second extrinsic information is stored to a different bank in the memory using the misaligned operation phases.Type: GrantFiled: September 9, 2010Date of Patent: May 6, 2014Assignee: QUALCOMM IncorporatedInventors: Zhiqiang Cui, Iwen Yao, Qiang Huang
-
Patent number: 8687746Abstract: Systems, methods, devices, and computer program products are described for Turbo decoding in a wireless communication system. Turbo encoded wireless signals may be received and demodulated, and forwarded to a branch metric calculator. The branch metric calculator may calculate a set of branch metrics for the demodulated signal. A state metric unit may receive the set of branch metrics and a previously calculated set of state metrics. The state metric unit may perform various comparisons of the set of state metrics before the received set of branch metrics is added to a portion of the state metrics identified through the comparisons.Type: GrantFiled: May 27, 2010Date of Patent: April 1, 2014Assignee: QUALCOMM IncorporatedInventors: Zhiqiang Cui, Iwen Yao, Qiang Huang
-
Patent number: 8572332Abstract: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.Type: GrantFiled: March 16, 2009Date of Patent: October 29, 2013Assignee: Qualcomm IncorporatedInventors: Ali RostamPisheh, Raghu N. Challa, Iwen Yao, Davie J. Santos, Mrinal M. Nath
-
Patent number: 8520571Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.Type: GrantFiled: March 2, 2009Date of Patent: August 27, 2013Assignee: Qualcomm IncorporatedInventors: Arunava Chaudhuri, Iwen Yao, Jeremy H. Lin, Ali RostamPisheh, Raghu Challa, Hemanth Sampath, Megan Wu, Joseph Zanotelli, Mrinal Nath
-
Patent number: 8458380Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.Type: GrantFiled: March 2, 2009Date of Patent: June 4, 2013Assignee: Qualcomm IncorporatedInventors: Arunava Chaudhuri, Iwen Yao, Jeremy H. Lin, Remi Gurski, Kevin W. Yen
-
Patent number: 8331892Abstract: A technique for performing AGC and DC compensation in a receiver. The receiver comprises an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain based on the energy estimation; a first DC compensation loop for finely adjusting the DC component of the received signal in fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting the DC component of the received signal. Three modes of AGC operations: In Acquisition, iterations of FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during signal timing detection. In Connected, long energy estimation, RF device gain adjustment, and STM fine and coarse DC adjustments are performed during superframe preamble. In Sleep, FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during superframe preamble.Type: GrantFiled: March 5, 2009Date of Patent: December 11, 2012Assignee: Qualcomm IncorporatedInventors: Tamer A. Kadous, Iwen Yao, Jibing Wang, Weihong Jing, Yong Li
-
Publication number: 20120249346Abstract: A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed.Type: ApplicationFiled: June 11, 2012Publication date: October 4, 2012Applicant: QUALCOMM IncorporatedInventors: Atul A. Salvekar, Young Geun Cho, Jia Tang, Shantanu Khare, Ming-Chieh Kuo, Iwen Yao
-
Patent number: 8199034Abstract: A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed.Type: GrantFiled: April 20, 2010Date of Patent: June 12, 2012Assignee: QUALCOMM IncorporatedInventors: Atul A. Salvekar, Young Geun Cho, Jia Tang, Shantanu Khare, Ming-Chieh Kuo, Iwen Yao
-
Publication number: 20120066566Abstract: A method for accessing extrinsic information in a turbo decoder is disclosed. Operation phases for Forward State Metric Calculators (FSMCs) and Reverse State Metric Calculators (RSMCs) in multiple maximum a posteriori probability (MAP) decoders are misaligned differently based on whether a current half iteration is even or odd. First extrinsic information is read from a memory into the FSMCs and RSMCs using the misaligned operation phases. Second extrinsic information is determined using the MAP decoders. Each row of the second extrinsic information is stored to a different bank in the memory using the misaligned operation phases.Type: ApplicationFiled: September 9, 2010Publication date: March 15, 2012Applicant: QUALCOMM IncorporatedInventors: Zhiqiang Cui, Iwen Yao, Qiang Huang
-
Publication number: 20110292849Abstract: Systems, methods, devices, and computer program products are described for Turbo decoding in a wireless communication system. Turbo encoded wireless signals may be received and demodulated, and forwarded to a branch metric calculator. The branch metric calculator may calculate a set of branch metrics for the demodulated signal. A state metric unit may receive the set of branch metrics and a previously calculated set of state metrics. The state metric unit may perform various comparisons of the set of state metrics before the received set of branch metrics is added to a portion of the state metrics identified through the comparisons.Type: ApplicationFiled: May 27, 2010Publication date: December 1, 2011Applicant: QUALCOMM IncorporatedInventors: Zhiqian Cui, Iwen Yao, Qiang Huang
-
Publication number: 20110254714Abstract: A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed.Type: ApplicationFiled: April 20, 2010Publication date: October 20, 2011Applicant: QUALCOMM IncorporatedInventors: Atul A. Salvekar, Young Geun Cho, Jia Tang, Shantanu Khare, Ming-Chieh Kuo, Iwen Yao
-
Publication number: 20100184397Abstract: A technique for performing AGC and DC compensation in a receiver. The receiver comprises an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain based on the energy estimation; a first DC compensation loop for finely adjusting the DC component of the received signal in fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting the DC component of the received signal. Three modes of AGC operations: In Acquisition, iterations of FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during signal timing detection. In Connected, long energy estimation, RF device gain adjustment, and STM fine and coarse DC adjustments are performed during superframe preamble. In Sleep, FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during superframe preamble.Type: ApplicationFiled: March 5, 2009Publication date: July 22, 2010Applicant: QUALCOMM IncorporatedInventors: Tamer A. Kadous, Iwen Yao, Jibing Wang, Weihong Jing, Yong Li
-
Publication number: 20090248920Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.Type: ApplicationFiled: March 2, 2009Publication date: October 1, 2009Applicant: QUALCOMM IncorporatedInventors: Arunava Chaudhuri, Iwen Yao, Jeremy H. Lin, Remi Gurski, Kevin W. Yen
-
Publication number: 20090249134Abstract: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.Type: ApplicationFiled: March 16, 2009Publication date: October 1, 2009Applicant: QUALCOMM IncorporatedInventors: Ali RostamPisheh, Raghu N. Challa, Iwen Yao, Davie J. Santos, Mrinal M. Nath
-
Publication number: 20090248774Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.Type: ApplicationFiled: March 26, 2009Publication date: October 1, 2009Applicant: QUALCOMM IncorporatedInventors: Arunava Chaudhuri, Hemanth Sampath, Iwen Yao, Jeremy H. Lin, Raghu N. Challa, Min Wu
-
Publication number: 20090245334Abstract: A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.Type: ApplicationFiled: October 30, 2008Publication date: October 1, 2009Applicant: QUALCOMM IncorporatedInventors: Arunava Chaudhuri, Iwen Yao, Jeremy H. Lin, Remi Gurski
-
Publication number: 20090245192Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.Type: ApplicationFiled: March 2, 2009Publication date: October 1, 2009Applicant: QUALCOMM IncorporatedInventors: Arunava Chaudhuri, Iwen Yao, Jeremy H. Lin, Ali Rostampisheh, Raghu Challa, Hamanth Sampath, Min Wu, Joseph Zanotelli, Mrinal M. Nath