Patents by Inventor Izumi Ishida

Izumi Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230246108
    Abstract: A transistor includes a bottom gate insulating film, an oxide semiconductor film, a top gate insulating film, a top gate electrode, a first interlayer insulating film, a source electrode, and a drain electrode, wherein the first interlayer insulating film contains carbon atoms, oxygen atoms, hydrogen atoms, and silicon atoms, hydrogen contained in the first interlayer insulating film has a higher concentration than hydrogen contained in the top gate insulating film, and oxygen contained in the first interlayer insulating film has a lower concentration than oxygen contained in the top gate insulating film.
    Type: Application
    Filed: April 28, 2020
    Publication date: August 3, 2023
    Inventors: IZUMI ISHIDA, YUJIRO TAKEDA, Shinji NAKAJIMA
  • Publication number: 20220190000
    Abstract: A display device, includes: a first gate electrode; a lower insulating film; a lower gate insulating film including a metal oxide film; and an oxide semiconductor layer, all of which are provided on a substrate in a stated order; and a first transistor provided on the substrate and including the oxide semiconductor layer, the first transistor including one or more first transistors, the first transistor including: a first channel region; a first conductor region holding the first channel region; and the first gate electrode across the lower gate insulating film from the first channel region, and between the lower insulating film and the first gate electrode, a clearance being provided, and the clearance being filled with the lower gate insulating film.
    Type: Application
    Filed: April 15, 2019
    Publication date: June 16, 2022
    Inventors: IZUMI ISHIDA, MASATOMO HONJO
  • Patent number: 11342362
    Abstract: A display device includes an active matrix substrate, wherein the active matrix substrate is layered with a base insulating film, a first metal layer, a metal oxide layer, a first inorganic insulating film, an oxide semiconductor layer, a second inorganic insulating film, a second metal layer, an interlayer insulating layer, and a third metal layer in order from a lower layer, and the active matrix substrate includes a first transistor configured of a first bottom gate electrode, a top gate electrode, and a source electrode and a drain electrode formed by the third metal layer, the source electrode and the drain electrode are respectively electrically connected to a source region and a drain region of the oxide semiconductor layer, the first bottom gate electrode is overlapped with the oxide semiconductor layer, and a metal of the first metal layer is different from a metal of the metal oxide layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 24, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Izumi Ishida, Hirohiko Nishiki, Yujiro Takeda
  • Patent number: 11028270
    Abstract: [Problem] To provide a composition for a black matrix which is a material suitable for manufacturing a black matrix, which is suitable for a high luminance display device structure and has high heat resistance and high light-shielding properties. [Means for Solution] The present invention uses a composition for a black matrix comprising: (I) a black colorant containing carbon black having a volume average particle diameter of 1 to 300 nm; (II) a siloxane polymer to be obtained by hydrolyzing and condensing a silane compound represented by a prescribed formula in the presence of an acidic or basic catalyst; (III) surface modified silica fine particles; (IV) a thermal base generator; and (V) a solvent.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: June 8, 2021
    Assignee: Merck Patent GmbH
    Inventors: Hirohiko Nishiki, Tohru Okabe, Izumi Ishida, Shogo Murashige, Atsuko Noya, Toshiaki Nonaka, Naofumi Yoshida
  • Publication number: 20210020662
    Abstract: A display device includes an active matrix substrate, wherein the active matrix substrate is layered with a base insulating film, a first metal layer, a metal oxide layer, a first inorganic insulating film, an oxide semiconductor layer, a second inorganic insulating film, a second metal layer, an interlayer insulating layer, and a third metal layer in order from a lower layer, and the active matrix substrate includes a first transistor configured of a first bottom gate electrode, a top gate electrode, and a source electrode and a drain electrode formed by the third metal layer, the source electrode and the drain electrode are respectively electrically connected to a source region and a drain region of the oxide semiconductor layer, the first bottom gate electrode is superimposed over the oxide semiconductor layer, and a metal of the first metal layer is different from a metal of the metal oxide layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 21, 2021
    Inventors: IZUMI ISHIDA, HIROHIKO NISHIKI, YUJIRO TAKEDA
  • Patent number: 10879064
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Nakajima, Hirohiko Nishiki, Hirohide Mimura, Yuhichi Saitoh, Yujiro Takeda, Shogo Murashige, Izumi Ishida, Tohru Okabe
  • Publication number: 20200277494
    Abstract: [Problem] To provide a composition for a black matrix which is a material suitable for manufacturing a black matrix, which is suitable for a high luminance display device structure and has high heat resistance and high light-shielding properties. [Means for Solution] The present invention uses a composition for a black matrix comprising: (I) a black colorant containing carbon black having a volume average particle diameter of 1 to 300 nm; (II) a siloxane polymer to be obtained by hydrolyzing and condensing a silane compound represented by a prescribed formula in the presence of an acidic or basic catalyst; (III) surface modified silica fine particles; (IV) a thermal base generator; and (V) a solvent.
    Type: Application
    Filed: December 7, 2017
    Publication date: September 3, 2020
    Inventors: Hirohiko NISHIKI, TOHRU OKABE, IZUMI ISHIDA, SHOGO MURASHIGE, Atsuko NOYA, Toshiaki NONAKA, Naofumi YOSHIDA
  • Patent number: 10690975
    Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost. An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 23, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Publication number: 20200194254
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 18, 2020
    Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Hirohide MIMURA, Yuhichi SAITOH, Yujiro TAKEDA, Shogo MURASHIGE, Izumi ISHIDA, Tohru OKABE
  • Patent number: 10685598
    Abstract: A wiring delay is prevented or reduced by lowering a wiring resistance without making a wire wider. The present invention includes: a light blocking film (102); a light-transmitting film (106); and a first wiring layer (105A) which serves as part of a wire configured to electrically control an amount of transmitted light for each pixel, the first wiring layer (105A) being provided over the light blocking film (102), and the light-transmitting film (106) being provided over the first wiring layer (105A) so as to cover a side surface of the first wiring layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 16, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Patent number: 10529743
    Abstract: Disclosed is an active matrix substrate that includes a plurality of TFTs. The active matrix substrate 11 includes a substrate 100, TFTs, a light transmission film 204, and a protection film Cap4. The TFTs are provided on the substrate 100 so as to correspond to a plurality of pixels, respectively. The light transmission film 204 is provided between the TFTs and the substrate 100. The protection film Cap4 covers an end surface 204b of the light transmission film 204, the end surface 204b being not parallel with the substrate 100. The TFT includes a gate electrode, a gate insulating film, a semiconductor film, a drain electrode, and a source electrode. The protection film Cap4 is arranged between the light transmission film 204 and the semiconductor film of the TFT.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shogo Murashige, Izumi Ishida, Tomohiro Kosaka, Tohru Okabe, Takeshi Hara, Hirohiko Nishiki
  • Publication number: 20190113813
    Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost. An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.
    Type: Application
    Filed: March 24, 2017
    Publication date: April 18, 2019
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Shinji NAKAJIMA, Izumi ISHIDA, Shogo MURASHIGE
  • Publication number: 20190103052
    Abstract: A wiring delay is prevented or reduced by lowering a wiring resistance without making a wire wider. The present invention includes: a light blocking film (102); a light-transmitting film (106); and a first wiring layer (105A) which serves as part of a wire configured to electrically control an amount of transmitted light for each pixel, the first wiring layer (105A) being provided over the light blocking film (102), and the light-transmitting film (106) being provided over the first wiring layer (105A) so as to cover a side surface of the first wiring layer.
    Type: Application
    Filed: March 27, 2017
    Publication date: April 4, 2019
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Shinji NAKAJIMA, Izumi ISHIDA, Shogo MURASHIGE
  • Publication number: 20190081081
    Abstract: Disclosed is an active matrix substrate that includes a plurality of TFTs. The active matrix substrate 11 includes a substrate 100, TFTs, a light transmission film 204, and a protection film Cap4. The TFTs are provided on the substrate 100 so as to correspond to a plurality of pixels, respectively. The light transmission film 204 is provided between the TFTs and the substrate 100. The protection film Cap4 covers an end surface 204b of the light transmission film 204, the end surface 204b being not parallel with the substrate 100. The TFT includes a gate electrode, a gate insulating film, a semiconductor film, a drain electrode, and a source electrode. The protection film Cap4 is arranged between the light transmission film 204 and the semiconductor film of the TFT.
    Type: Application
    Filed: July 7, 2016
    Publication date: March 14, 2019
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: SHOGO MURASHIGE, IZUMI ISHIDA, TOMOHIRO KOSAKA, TOHRU OKABE, TAKESHI HARA, HIROHIKO NISHIKI
  • Patent number: 10209592
    Abstract: An active matrix substrate includes an insulating substrate in which light-transmitting areas and a light-shielding area are formed. The active matrix substrate further includes: a light-shielding film formed in the light-shielding area on the insulating substrate, with a transparent base material containing carbon particles, the light shielding film being colored with the carbon particles; an inorganic film formed on the light-shielding film; light-transmitting films formed in the light-transmitting areas on the insulating substrate, with a transparent base material containing transparent oxidized carbon particles; gate lines provided on the inorganic film; a gate insulating film provided on the gate lines; thin film transistors provided in matrix on the gate insulating film; and data lines provided on the light-shielding film to intersect with the gate lines. The data lines are electrically connected with the thin film transistors.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 19, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Hara, Tomohiro Kosaka, Izumi Ishida, Shogo Murashige
  • Publication number: 20180254293
    Abstract: An active matrix substrate 10 includes: an insulating substrate 110; a first conductive film 130 formed on the insulating substrate 110; a light-transmitting film 114 formed on the insulating substrate 110 so that the light-transmitting film 114 covers the first conductive film 130; a second conductive film 140 formed on the light-transmitting film 114; a first insulating layer 115 formed on the light-transmitting film 114 so that the first insulating layer 115 covers the second conductive film 140; a semiconductor film 170 formed on the first insulating layer 115; and a third conductive film 150 formed on the first insulating layer 115 and the semiconductor film 170. The first conductive film 130 and the second conductive film 140 are electrically connected via the third conductive film 150.
    Type: Application
    Filed: September 7, 2016
    Publication date: September 6, 2018
    Inventors: TOHRU OKABE, HIROHIKO NISHIKI, TAKESHI HARA, TOMOHIRO KOSAKA, IZUMI ISHIDA, SHOGO MURASHIGE
  • Publication number: 20180210306
    Abstract: An active matrix substrate includes an insulating substrate 100 in which light-transmitting areas and a light-shielding area are formed. The active matrix substrate further includes: a light-shielding film 201 formed in the light-shielding area on the insulating substrate 100, with a transparent base material containing carbon particles, the light shielding film being colored with the carbon particles; an inorganic film 202 formed on the light-shielding film; light-transmitting films 204 formed in the light-transmitting areas on the insulating substrate, with a transparent base material containing transparent oxidized carbon particles; gate lines 111 provided on the inorganic film; a gate insulating film 101 provided on the gate lines; thin film transistors 300 provided in matrix on the gate insulating film; and data lines provided on the light-shielding film to intersect with the gate lines. The data lines are electrically connected with the thin film transistors 300.
    Type: Application
    Filed: July 7, 2016
    Publication date: July 26, 2018
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: TOHRU OKABE, HIROHIKO NISHIKI, TAKESHI HARA, TOMOHIRO KOSAKA, IZUMI ISHIDA, SHOGO MURASHIGE
  • Publication number: 20180188575
    Abstract: An active matrix substrate includes an insulating substrate (100); a surface coating film (110) that covers at least a part of a surface of the insulating substrate; an insulating light-transmitting film (204) provided on the insulating substrate including the surface coating film; gate lines; a gate insulating film; thin film transistors; data lines; and lead-out lines (115). In a peripheral portion of the insulating substrate, an area where the insulating light-transmitting film is not provided is formed. The lead-out line is provided so as to intersect with an outer circumference end of the insulating light-transmitting film, when viewed in a direction vertical to the insulating substrate. In the area where the insulating light-transmitting film is not provided, the surface coating film is also provided on a part in contact with the outer circumference end of the insulating light-transmitting film.
    Type: Application
    Filed: July 7, 2016
    Publication date: July 5, 2018
    Inventors: TOMOHIRO KOSAKA, TAKESHI HARA, TOHRU OKABE, IZUMI ISHIDA, SHOGO MURASHIGE, KENICHI KITOH, HIROHIKO NISHIKI
  • Patent number: 9853164
    Abstract: This semiconductor device is provided with: a semiconductor film that comprises an oxide semiconductor, and includes a channel region; a first inorganic insulating film formed on the semiconductor film; a first organic insulating film formed on the first inorganic insulating film; and an inorganic film group. The inorganic film group has: a first electrode comprising an inorganic conductive film formed on the first organic insulating film; a second inorganic insulating film formed on the first electrode; and a second electrode that comprises an inorganic conductive film formed on the second inorganic insulating film, and is electrically connected to the semiconductor film via openings formed in such a manner as to penetrate the first inorganic insulating film, the first organic insulating film, the first electrode and the second inorganic insulating film. The first organic insulating film is disposed between the first inorganic insulating film and the inorganic film group.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 26, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Hara, Hirohiko Nishiki, Izumi Ishida, Shogo Murashige
  • Publication number: 20150303307
    Abstract: This semiconductor device is provided with: a semiconductor film that comprises an oxide semiconductor, and includes a channel region; a first inorganic insulating film formed on the semiconductor film; a first organic insulating film formed on the first inorganic insulating film; and an inorganic film group. The inorganic film group has: a first electrode comprising an inorganic conductive film formed on the first organic insulating film; a second inorganic insulating film formed on the first electrode; and a second electrode that comprises an inorganic conductive film formed on the second inorganic insulating film, and is electrically connected to the semiconductor film via openings formed in such a manner as to penetrate the first inorganic insulating film, the first organic insulating film, the first electrode and the second inorganic insulating film. The first organic insulating film is disposed between the first inorganic insulating film and the inorganic film group.
    Type: Application
    Filed: September 30, 2013
    Publication date: October 22, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takeshi HARA, Hirohiko NISHIKI, Izumi ISHIDA, Shogo MURASHIGE