Patents by Inventor Izumi Okamoto

Izumi Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5742097
    Abstract: Two modules, each of which has a plurality of memory IC chips installed therein, are stacked to form a module unit. Furthermore, a plurality of the module units are installed on a mother board so as to form a multilevel semiconductor integrated circuit device. By further stacking a specific module containing an IC chip for replacing the functions of a defective chip, a repair process can be conducted more easily and efficiently. Alternatively, instead of the module units, a plurality of TAB packages stacked in a multilayer structure are installed on the mother board. Outer leads of each of the TAB packages and terminal pads on the circuit board are respectively connected to each other in a one-to-one way. Thus, only a defective TAB package need be taken away and consequently, efficiency in the repair process further improves.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: April 21, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hayami Matsunaga, Masao Iwata, Yoshikazu Suehiro, Hideo Kurokawa, Izumi Okamoto
  • Patent number: 5652462
    Abstract: Two modules, each of which has a plurality of memory IC chips installed therein, are stacked to form a module unit. Furthermore, a plurality of the module units are installed on a mother board so as to form a multilevel semiconductor integrated circuit device. By further stacking a specific module containing an IC chip for replacing the functions of a defective chip, a repair process can be conducted more easily and efficiently. Alternatively, instead of the module units, a plurality of TAB packages stacked in a multilayer structure are installed on the mother board. Outer leads of each of the TAB packages and terminal pads on the circuit board are respectively connected to each other in a one-to-one way. Thus, only a defective TAB package need be taken away and consequently, efficiency in the repair process further improves.
    Type: Grant
    Filed: July 21, 1995
    Date of Patent: July 29, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hayami Matsunaga, Masao Iwata, Yoshikazu Suehiro, Hideo Kurokawa, Izumi Okamoto
  • Patent number: 5490041
    Abstract: A plurality of memory modules are stacked so as to form a multilayer integrated memory circuit. All of the memory modules have a plurality of bare memory IC chips mounted thereon, and have the same structure, the same circuit configuration and the same terminal arrangement in lead frames with each other. Each of the memory modules to be stacked in each layer is rotated by 90.degree., 180.degree. or 270.degree. before being stacked and connected to each other. Thus, in the multi-layered memory circuit, it is possible that signals can be selectively input/output to/from a particular layer in the multilayer structure, although the lead terminals of each of memory modules has the same configuration and the same arrangement with each other. As a result, a small-size integrated memory circuit device with a large memory-capacity can be provided, which can be fabricated easily and efficiently. A higher processing speed of digital computers can be also achieved.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: February 6, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hitonobu Furukawa, Hayami Matsunaga, Yoshikazu Suehiro, Masao Iwata, Takeo Yasuho, Izumi Okamoto, Kazuo Takeda, Shuji Ida
  • Patent number: 5400599
    Abstract: Gas displacement volumes of a high temperature chamber and a middle temperature chamber in a high temperature portion of a hot gas machine are different. Alternatively, a gas displacement volume of a low temperature chamber and a middle temperature chamber in a low temperature portion are different.
    Type: Grant
    Filed: December 8, 1992
    Date of Patent: March 28, 1995
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroshi Sekiya, Masahisa Otake, Junji Matsue, Ryouichi Katohno, Toshikazu Ishihara, Izumi Okamoto, Yoshiaki Kurosawa, Mitsuhiko Ishino
  • Patent number: 4595934
    Abstract: An improved thermal head for thermal recording includes an array of a plurality of heat generator elements arranged in a direction first, and a plurality of semiconductor chips each thereof including a plurality of transistors for selectively energizing the plural heat generator elements. An array of electrode terminals including the individual electrode terminals of the plurality of transistors each thereof being connected to one electrode of each of the plurality of heat generator elements are formed on one of the major surfaces of each of the semiconductor chips in a second direction substantially perpendicular to the first direction of the heat generator element array. The thermal head further comprises a flexible film associated with each of the semiconductor chips and having a slot or recess surrounding the electrode terminal array.
    Type: Grant
    Filed: June 6, 1984
    Date of Patent: June 17, 1986
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Shoji Arai, Izumi Okamoto, Masayoshi Mihata