Abstract: A process dispatch method for use in a multiprocessor system in which each process mounts a cache memory is disclosed. When a process A is dispatched, all the processes in execution having the lowest priority are selected. If only one process is selected, the process A is dispatched to the processor executing this selected process. If a plurality of processes are selected and if the processors executing the selected processes include the processor which executed the process A immediately before, the process A is dispatched to this processor.

Abstract: A priority selector of a system including a plurality of processors and a shared source commonly used by the processors sets a priority of requests supplied from the processors for using the shared source and supplies a use permission to a single processor. The priority selector has a plurality of lock request priority setting circuits corresponding to the processors and a request selector. When a contention occurs between an own request from a processor and other request from another processor, the corresponding lock request priority setting circuit upgrades the non-permitted own request as a high priority request when the other request is permitted, and downgrades a following own request as a low priority request when the own request is accepted.

Abstract: A scan operation executing system includes a command decoding unit and a scan mode setting unit. The command decoding unit is initialized together with a diagnostic control unit in accordance with a diagnostic activation signal from a diagnostic processor, outputs a reset signal in response to a diagnostic command for a scan operation execution request subsequent to the diagnostic activation signal, and outputs a reset signal in response to a diagnostic command for a scan mode reset request. The scan mode setting unit is set by a set signal from the command decoding unit to supply a scan mode signal to a processing unit of a main processor and is reset by the reset signal to disconnect the scan mode signal.

Abstract: An erroneous selection signal detecting circuit in a data transfer system. Conventional error detecting systems may not be capable of detecting errors in the selection signal generating circuit using available parity of checksum procedures. The selector means in the present invention selects one of a plurality of input signals on the basis of selection information. This information is applied both to appropriate selection circuits and to two additional selecting circuits also continually receiving fixed data input values. The outputs from these additional circuits are compared to the selection signals through EXCLUSIVE-OR gates, a particular logical indication from the EXCLUSIVE-OR gates indicating a malfunction.

Abstract: In an intercommunication network for use in transmitting a transmission request from a first processor to a second processor, the first processor sends a first processor number preassigned thereto through a system bus to the second processor which holds a communicable processor number corresponding to the first processor number and which detects whether or not the first processor number indicates the first processor by monitoring correspondence between the first processor number and the communicable processor number. A destination processor number assigned to the second processor may not be transmitted from the first processor because identification is made in the second processor. Thus, no destination processor number is administrated in the first processor. The first and the second processors may belong to a lower rank and an upper rank, respectively, and may be an input/output processor and an execution processor unit, respectively.

Abstract: In a multiprocessor system in which at least three processors are connected to a system bus by way of which data and source and destination processor identification numbers are exchanged between source and destination processors. A third processor receives the same data and the same source and destination processor ID numbers as those received by the destination processor. Each processor detects an error in data being transmitted to the bus and detects an error in data being received therefrom. A transmit error bit is stored into a transmit error bit register in response to the detection of error in the transmitted data and a receive error bit is stored into a receive error bit register in response to the detection of error in the received data. The processor ID numbers are also stored in registers in each processor in response to the detection of the errors.

Abstract: A system applicable to a multiprocessor system for processing communications among central processing units (CPUs) in which, when one of the CPUs has sent process requests to a plurality of the other CPUs at the same time, end-of-process requests appearing asynchronously to each other are processed. If the CPUs to which the requests are meant for have ended processing normally, ending of all the kinds of processing can be completed within a short period of time and without restoring to complicated firmware processing. Even if the end condition at any CPU is abnormal, the firmware processing is simplified because the end reports are selectively returned based on a predetermined priority order.

Abstract: In a memory access system used for receiving a logical address and a memory request, translating the logical address into a real address, and accessing a memory by using the real address, a non-address-translation portion, which is not an object to be translated, in the logical address is transmitted in advance to the memory through an address signal line when the memory request associated with the logical address supplied to the memory is generated, and an address-translation portion, which is an object to be translated, in the logical address is transmitted to the memory through the address signal line upon completion of address translation of the address-translation portion.