Abstract: A radio telephone system clock is resynchronized in idle mode in relation to an associated transmitter/receiver station system clock, e.g. a fixed part for the DECT system, by counting the number of clock pulses between two detections of the preamble and the sync word of the DECT signal and using the counter status for determining a correction value. In addition to the system clock, a clock device comprises at least a further clock. A counter device counts the clock pulses from the clock, and a control device monitors the status of the counter device and activates the detecting means in response thereto when the status corresponds to the estimated arrival of the next preamble. The control device is adapted to register the status of the counter device when the detecting means detect the preamble and to correct the activation time of the detecting means for the next preamble for detection in response thereto.

Abstract: A quadrature down converter comprises two channels, each of said channels comprising two parallel signal paths. Each of said signal path comprises a mixer mixing the signal for down conversion with an oscillator signal. In the in-phase channel the mixers receive the oscillator signal shifted 0.degree. and 180.degree. in phase, respectively. In the quadrature-phase channel the mixers receive the oscillator signal shifted 90.degree. and 270.degree. in phase, respectively. By filtering and combining (adding/subtracting) the signals from the signal paths in each of said channels, the disturbing second order terms from the mixers may be substantially eliminated.

Abstract: A system clock of a radio telephone is adjusted in relation to an associated transmitter/receiver station system clock by detecting a predetermined part (SYNC word) which occurs periodically in a digital signal. A clock signal having pulses synchronous with the system clock signal of the radio telephone is formed. The clock pulses in the clock signal are counted between the detection of two predetermined parts in the digital signal, and the system clock is corrected in response to the number of pulses between the detection of said two predetermined parts in the digital signal.

Abstract: A DC compensation module for suppressing the DC content of a signal containing a periodic sequence comprises a signal transport path (10), a signal compensation path (13) and a combination unit (11). The signal transport path (10) transfers the signal from the input of the module to an input on the combination unit (11). The signal compensation path (13) is coupled to another input on the combination unit (11), and is provided with a low pass filter (14; 17) filtering a signal transferred via the signal compensation path (13). The low pass filter (14; 17) of the signal compensation path (13) is provided with a notch (20) at a frequency corresponding to the period of the periodic signal. The combination unit (11) supplies a signal in response to the difference between the signals received from the signal transport path (10) and from the signal compensation path (13).

Abstract: A data clock signal for data in an incoming signal is generated by means of a clock recovery module. The incoming signal consists of a data burst having a periodic preamble followed by a data sequence. The clock recovery module comprises a first clock generator, a sampling device, a correlator, a control unit and a time registration device. The clock generator generates a clock signal having a first clock frequency which is a factor N higher than the frequency of the preamble. The sampling device samples the incoming signal at the first clock frequency. The correlator correlates the sampled signal with a predefined correlation word, the correlation between the incoming signal and the correlation word being represented as a correlation signal in the form of a series of discrete correlation signal values. The control unit detects local extreme values for the correlation signal.