Patents by Inventor J. Antonio Salcedo

J. Antonio Salcedo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methodology for storing and updating on-chip revision level
    Patent number: 8209654
    Abstract: Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: June 26, 2012
    Assignee: Exar Corporation
    Inventors: Tore Lennart Kellgren, J. Antonio Salcedo
  • METHODOLOGY FOR STORING AND UPDATING ON-CHIP REVISION LEVEL
    Publication number: 20110185337
    Abstract: Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.
    Type: Application
    Filed: January 22, 2010
    Publication date: July 28, 2011
    Applicant: EXAR CORPORATION
    Inventors: Tore Lennart Kellgren, J. Antonio Salcedo
  • Image sampling circuit with a blank reference combined with the video input
    Patent number: 6952240
    Abstract: A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor amplifier. In one embodiment, an ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier so that the zero level of the video signal is made to correspond to the zero level of the ADC.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: October 4, 2005
    Assignee: Exar Corporation
    Inventors: Richard L. Gower, Eric G. Hoffman, Bhupendra K. Ahuja, J. Antonio Salcedo
  • Low power wide bandwidth programmable gain CDS amplifier/instrumentation amplifier
    Patent number: 6573784
    Abstract: A method and circuitry for implementing programmable gain. More particularly, embodiments of the present invention provide an amplifier circuit which can be used as a CDS-amp or an instrumentation amplifier. Included is a two-stage amplifier, each stage having a few as one transistor. A current source biases one stage of the two-stage amplifier. A load resistor network couples to the two-stage amplifier and is configured to set gain values for the two-stage amplifier.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: June 3, 2003
    Assignee: Exar Corporation
    Inventors: Richard Leigh Gower, Bhupendra Kumar Ahuja, J. Antonio Salcedo
  • Low power wide bandwidth programmable gain CDS amplifier/instrumentation amplifier
    Publication number: 20030042975
    Abstract: A method and circuitry for implementing programmable gain. More particularly, embodiments of the present invention provide an amplifier circuit which can be used as a CDS-amp or an instrumentation amplifier. Included is a two-stage amplifier, each stage having a few as one transistor. A current source biases one stage of the two-stage amplifier. A load resistor network couples to the two-stage amplifier and is configured to set gain values for the two-stage amplifier.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Inventors: Richard Leigh Gower, Bhupendra Kumar Ahuja, J. Antonio Salcedo
  • Image sampling circuit with a black reference combined with the video input
    Publication number: 20020171773
    Abstract: A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor amplifier. In one embodiment, an ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier so that the zero level of the video signal is made to correspond to the zero level of the ADC.
    Type: Application
    Filed: May 18, 2001
    Publication date: November 21, 2002
    Inventors: Richard Gower, Eric Hoffman, Bhupendra Ahuja, J. Antonio Salcedo
  • Rising and falling edge aperture delay control circuit in analog front end of imaging system
    Patent number: 6424197
    Abstract: A programmable delay in an AFE of an imaging system which can vary both the pulse position and the pulse width. The pulse width and position are controlled by providing separate programmable delay circuits for the rising and falling edges of the desired timing signal. Combining logic then combines the outputs of the two delay circuits to produce an output clock with separately delayed rising and falling edges.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: July 23, 2002
    Assignee: Exar Corporation
    Inventors: J. Antonio Salcedo, Charles Rogers, Raphael Horton