Abstract: A system and a method to generate cellular automata based random number generators (CA-based RNGs) are presented A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t−1. The connections (or inputs) are selected to produce high entropy such that the RNG passes a standard suite of random number of tests, such as the DIEHARD suite. The RNGs may be implemented with field programmable gate arrays.

Abstract: System and method to emulate cellular automata based random number generators (CA-based RNGs) in software are presented. Also, system and method to automatically generate software emulators of CA-based RNG are presented. A CA-based RNG is where an output of each cell of the CA at time t is dependent on inputs from any cells of the CA (including perhaps itself) at time t−1. The simulation software are high performing due to parallel simulation of multiple cells of the CA rather than emulating behaviors of cells individually and then combining the results. The simulation software may also include parallel site spacing capabilities.

Abstract: An iterative array of identical cells to implement a crossover function in a genetic algorithm. Each function cell receives two input values and two select values that determine which input value is outputted. By creating an array of these cells, two sets of information of any size can be rapidly and accurately merged to form one set composed of elements of both sets. The cellular array uses identical, repeated cells to implement the crossover function according to precise guidelines. These guidelines are that no data is to be repeated and no data is to be lost, while retaining the order of the parent chromosomes used in crossover.

Abstract: 100110018-1 A method for a user to program an electronic system not having a QWERTY keypad. A user-generated electronic mail message is originated via a remote keypad. The electronic mail message includes user-selected preference data, and is communicated to an electronic mail destination. The user-selected preference data is automatically extracted from the electronic mail message, transmitted to the electronic system, and used to configure the electronic system.

Abstract: A fitness function circuit for computing a fitness value for a trial solution to a set covering problem accelerates the execution speed of a genetic algorithm provided with a matrix circuit for outputting a column signal covered by a row signal corresponding to a bit in a chromosome, a column signal counter for counting column signals, a subtractor for calculating a difference between a counted number of column signals and a number of all elements and outputting the difference as a number of uncovered elements, a carry-save-adder for outputting a number of valid row signals as a chromosome cost, an aggregate cost register for holding the number of uncovered elements as a more significant portion of a total cost and the chromosome cost as a less significant portion of the total cost and outputting the total cost, an inverter for inverting a value of the total cost and outputting an inverted value as a fitness value.

Abstract: A multi-purpose non-problem-specific hardware-based framework for the execution of a genetic algorithm (GA) accelerates the execution speed of a GA through the implementation of hardware-based non-problem-specific functions of population memory, first and second chromosome registers, crossover module, mutation operator, and survival comparator. The non-problem-specific aspect of the hardware-based framework turns problem-specific without changing the contents of the framework once a problem-specific fitness function circuit is included for evaluating chromosomal data representing a potential problem solution. The hardware-based framework is thus applicable to a variety of problem-specific aspects of the problem-specific fitness function circuit.

Abstract: The present invention provides a processor synthesis system and a processor synthesis method which enable a designer to synthesize a CPU that does not depend on a specific process technology and has the bit width customized to the requirements of the specific application. The processor synthesis method according to the present invention comprises steps of generating and outputting processor definition information to define a CPU based on primary parameters entered by the designer; generating a compiler and an assembler for generating an instruction code for the CPU defined by the processor definition information; and executing simulation using the instruction code output by the generated compiler and the assembler so as to facilitate optimization of the designed CPU and reduce development costs.

Abstract: A method for operating a FPGA to compute a function whose optimum represents the preferred partitioning of a graph having a plurality of vertices connected by edges. The FPGA is configured to provide a partition state register having a plurality of cells. Each cell corresponds to one of the vertices in the graph and is used to store a number indicative of the partition to which the corresponding vertex is currently assigned. The algorithm for determining the optimum partition computes a cost function having two components. The assignment of the vertices to the various partitions is made such that this cost function is minimized. For any given assignment of the vertices, the FPGA computes the cost function using two circuits that are configured from the FPGA. The first circuit computes the number of edges that connect vertices belonging to different partitions. The second circuit computes a number that represents the extent to which the various partitions differ from one another in size.

Abstract: A field compositor, with a regular and systematic structure, that merges fields of data together to compose new data words. Starting from a basic cell, the field compositor merges longer words by connecting more of the basic cells together in a systematic and orderly fashion. The cells are connected in a regular structure so that routing data through the compositor can be done in a similarly regular manner. The basic cell of a one-dimensional regular array has three control inputs to control two outputs, one being a data output; depending on the logic levels presented to the three inputs, data from the first or the second set of data are selected to be the data output of the cell. The basic cell of a two-dimension regular array has five control inputs and two outputs, one being a data output; depending on the logic levels of the five control inputs, data from the first or the second set of data are selected to be the data output of the cell.

Abstract: A leading zero detector includes at least one asynchronous cell for receiving an input word and providing a data output indicative of the number of leading zeros in the input word. The cell may be cascaded with a plurality of like cells to define an array. The array is expandable for use with an input word of any bit width.