Abstract: A system and method of characterizing a device under test wherein a signal is injected into the device under test, the response to the injected signal is measured to determine the impedance of the device under test in the frequency domain, the impedance is converted to the time domain, and the voltage noise of the device under test is calculated based on the impedance of the device under test in the time domain.

Abstract: A method of predicting electrical behavior of a device comprises the steps of representing at least one balanced matching network having a balanced input port and a balanced output port and further representing a connection between the matching network an a balanced output port and a balanced input port of a device. A matching network S-parameter matrix is calculated and a device S-parameter matrix is obtained either through a measurement or from a model. A cascaded S-parameter matrix for the matching network in combination with the device is calculated, and from the resulting cascaded S-parameter matrix, a mixed-mode cascaded S-parameters may be extracted. The mixed-mode cascaded S-parameters assist a designer in predicting and analyzing the electrical behavior of the differential and single-ended ports as well as the electrical interaction therebetween.

Abstract: A method and apparatus for characterizing a device under test (“DUT”) calibrates a multiport test set and measures S-parameters [S] of the DUT. The method and apparatus further involves determining elements of a scalar orthogonal matrix [M] corresponding to terminals of the DUT and DUT modes of operation. The scalar orthogonal matrix [M] comprises a row of elements representing a single-ended terminal of the DUT, and four rows of elements representing a balanced terminal of the DUT. The S-parameters of the DUT are then transformed into mixed-mode S-parameters [Smm] according to Smm=MSM−1. A method of and apparatus for characterizing a DUT involves calibrating a multiport test set, coupling the DUT to the multiport test set, and measuring S-parameters of the DUT. The S-parameters are converted to a time domain representation and at least one of the S-parameters is convolved with a simulated input signal to generate an output response.

Abstract: A method of predicting electrical behavior of a device comprises the steps of representing at least one balanced matching network having a balanced input port and a balanced output port and further representing a connection between the matching network an a balanced output port and a balanced input port of a device. A matching network S-parameter matrix is calculated and a device S-parameter matrix is obtained either through a measurement or from a model. A cascaded S-parameter matrix for the matching network in combination with the device is calculated, and from the resulting cascaded S-parameter matrix, a mixed-mode cascaded S-parameters may be extracted. The mixed-mode cascaded S-parameters assist a designer in predicting and analyzing the electrical behavior of the differential and single-ended ports as well as the electrical Interaction therebetween.

Abstract: According to one embodiment of the invention, there is provided an N-port automatic calibration device comprising N-ports, wherein each port is adapted to be coupled to a port of an N-port multiport test set. The N-port automatic calibration device comprises a single-pole, N−1 throw switch having a single-pole coupled to a first port of the automatic calibration device and having each throw of the N−1 throws coupled to a corresponding port of the automatic calibration device. In addition, the N-port automatic calibration device comprises at least one single-pole, double-throw switch, having a single-pole coupled to a second port of the N-ports of the automatic calibration device, having a first throw coupled to a first load impedance, and having a second throw coupled to a throw of the N−1 throws of the single-pole, N−1 throw switch.

Abstract: According to one embodiment of the invention, there is provided an N-port automatic calibration device comprising N-ports, wherein each port is adapted to be coupled to a port of an N-port multiport test set. The N-port automatic calibration device comprises a single-pole, N−1 throw switch having a single-pole coupled to a first port of the automatic calibration device and having each throw of the N−1 throws coupled to a corresponding port of the automatic calibration device. In addition, the N-port automatic calibration device comprises at least one single-pole, double-throw switch, having a single-pole coupled to a second port of the N-ports of the automatic calibration device, having a first throw coupled to a first load impedance, and having a second throw coupled to a throw of the N−1 throws of the single-pole, N−1 throw switch.

Abstract: One embodiment of the invention comprises a multiport test set that characterizes a multiterminal DUT. The multiport test set comprises a plurality of ports, a signal generator that provides a test signal over a frequency range, a reference receiver coupled to the signal generator that measures the test signal to determine a reference value, and at least one test channel receiver that measures the test signal at each port of the multiport test set. The multiport test set further comprises a switching device, coupled between the signal generator, the plurality of ports of the multiport test set and the at least one test channel receiver, that couples the test signal to any port of the multiport test set and to the at least one test channel receiver.

Abstract: A switchable, dual channel frequency converter is provided. The converter includes a semiconductor body having formed as a monolithic microwave integrated circuit: a pair of input signal channels; a pair of output signal channels; and, a mixer and multiplexer means, disposed between the pair of input signal channels and the pair of output signal channels, for converting the frequency of signals fed to the pair of input signal channels to a different frequency and for directing the frequency converted signals to the pair of output signal channels selectively in accordance with a control signal. The mixer and multiplexer means includes: a pair of mixers coupled to the pair of input signal channels and a common local oscillator signal; and a multiplexer network. The mixers covert the radio frequency of the signals in the pair of input signal channels into a corresponding pair of intermediate frequency signal channels.

Abstract: A distributed circuit includes a plurality of pairs of cascode coupled first and second transistors with each transistor having base, emitter, and collector electrodes. The first transistor of each pair is disposed to have a first one of emitter and collector electrodes coupled to a reference potential and the second one of said transistors of each pair is disposed to have the base electrode coupled to a reference potential with the second one the collector and emitter electrodes of the first transistor of each pair being coupled to the emitter electrode of the corresponding second transistor of each pair. The network further includes an input propagation network disposed to successively couple the base electrode of each one of the first transistors of each pair of transistors to an input terminal and an output propagation network disposed to couple the collector electrodes of each one of the second transistors of each one of the pair of transistors to an output terminal of the circuit.

Abstract: A monopulse antenna system having a four quadrant array of antenna elements and a plurality of summing and differencing amplifiers coupled to the antenna elements for combining signals received by such antenna elements to provide such monopulse antenna with a sum antenna pattern, an azimuthal difference antenna pattern, and an elevation difference antenna pattern. The differencing amplifiers include a feedback network for increasing the common mode rejection ratio of the amplifier. The amplifiers includes a pair of transistors coupled to a voltage source through active loads and a common biasing network. The pair of transistors have electrodes connected to a common junction. A variable current source biasing network comprises a resistor voltage divider for producing an output voltage equal to a portion of a bias voltage produced at the common junction and a third transistor having a pair of electrodes coupled between the common junction and the voltage source.