Patents by Inventor J. Eric Ruetz
J. Eric Ruetz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8161355Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.Type: GrantFiled: February 11, 2009Date of Patent: April 17, 2012Assignee: MoSys, Inc.Inventors: Stephen Fung, Vithal Rao, Da-Guang Yu, J. Eric Ruetz, Chee T. Chua, Jawji Chen, Kameswara K. Rao
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Patent number: 8081521Abstract: A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.Type: GrantFiled: February 13, 2009Date of Patent: December 20, 2011Assignee: MoSys, Inc.Inventors: Chee T. Chua, Kameswara K. Rao, Vithal R. Rao, Jawji Chen, Da-Guang Yu, J. Eric Ruetz, Stephen Fung
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Publication number: 20100208530Abstract: A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: MoSys, Inc.Inventors: Chee T. Chua, Kameswara K. Rao, Vithal R. Rao, Jawji Chen, Da-Guang Yu, J. Eric Ruetz, Stephen Fung
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Publication number: 20100205504Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.Type: ApplicationFiled: February 11, 2009Publication date: August 12, 2010Applicant: Mosys, Inc.Inventors: Stephen Fung, Vithal Rao, Da-Guang Yu, J. Eric Ruetz, Chee T. Chua, Jawji Chen, Kameswara K. Rao
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Patent number: 6515536Abstract: A differential charge pump utilizing a common mode feedback circuit. The charge pump includes a dual reference current source and outputs a differential current signal by modifying currents routed to the outputs utilizing current paths having transistors maintained in the linear region within the current paths. The common mode feedback circuit includes differential transistors requiring a maximum power supply voltage of a common mode reference voltage plus a transistor threshold voltage.Type: GrantFiled: June 14, 2001Date of Patent: February 4, 2003Assignee: S3 Incorporated, Inc.Inventors: Guojin Liang, J. Eric Ruetz
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Publication number: 20010030572Abstract: A differential charge pump utilizing a common mode feedback circuit. The charge pump includes a dual reference current source and outputs a differential current signal by modifying currents routed to the outputs utilizing current paths having transistors maintained in the linear region within the current paths. The common mode feedback circuit includes differential transistors requiring a maximum power supply voltage of a common mode reference voltage plus a transistor threshold voltage.Type: ApplicationFiled: June 14, 2001Publication date: October 18, 2001Applicant: S3 IncorporatedInventors: Guojin Liang, J. Eric Ruetz
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Patent number: 6275097Abstract: A differential charge pump utilizing a common mode feedback circuit. The charge pump includes a dual reference current source and outputs a differential current signal by modifying currents routed to the outputs utilizing current paths having transistors maintained in the linear region within the current paths. The common mode feedback circuit includes differential transistors requiring a maximum power supply voltage of a common mode reference voltage plus a transistor threshold voltage.Type: GrantFiled: April 2, 1999Date of Patent: August 14, 2001Assignee: S3 Incorporated, Inc.Inventors: Guojin Liang, J. Eric Ruetz
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Patent number: 5319258Abstract: A programmable output driver circuit is provided having multiple drive capabilities for optimising noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.Type: GrantFiled: October 5, 1992Date of Patent: June 7, 1994Assignee: Samsung Semiconductor, Inc.Inventor: J. Eric Ruetz
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Patent number: 5254961Abstract: A crystal oscillator circuit has a sleep mode of operation that reduces power consumption while maintaining oscillation to provide for a fast transition to a normal mode of operation.Type: GrantFiled: October 13, 1992Date of Patent: October 19, 1993Assignee: Samsung Semiconductor, Inc.Inventor: J. Eric Ruetz
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Patent number: 5164889Abstract: A charge pump having gate control voltages multiplexed to gates of FET driver circuits to precisely control charge injected by the charge pump to a low pass filter network. Large capacitors between the supply voltages and the respective gate control voltage derived from the particular supply voltage provide greater noise immunity which further reduces phase errors introduced by injected charge variations. The large capacitors help to hold the gate voltages constant, further controlling the injected charge.Type: GrantFiled: October 10, 1991Date of Patent: November 17, 1992Assignee: Samsung Semiconductor, Inc.Inventor: J. Eric Ruetz
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Patent number: 5155384Abstract: A start-up circuit for a bias generating circuit includes a current source for providing a small charging current, and transistors for coupling the charging current to the bias generating circuit during power up to force the bias generating circuit into a steady-current state. The start-up circuit also uncouples the current source from the bias circuit after the bias generating circuit is forced into the steady-current state to prevent the charging current from affecting the operation of the bias generating circuit.Type: GrantFiled: May 10, 1991Date of Patent: October 13, 1992Assignee: Samsung Semiconductor, Inc.Inventor: J. Eric Ruetz
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Patent number: 5155453Abstract: An improved crystal oscillator and output circuit is disclosed. The oscillator has a normal operating mode and a low-power mode. In the low-power mode, a reduced current which is sufficient to maintain oscillation is supplied to the oscillator and the output circuit is disabled. The oscillator can subsequently be returned to normal mode and the output circuit enabled. Since the oscillator is never shut completely off, the time required to resume normal mode oscillations is reduced.Type: GrantFiled: May 23, 1991Date of Patent: October 13, 1992Assignee: Samsung Semiconductor, Inc.Inventor: J. Eric Ruetz
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Patent number: 5153534Abstract: A high-frequency voltage controlled oscillator includes a start-up circuit for preventing the oscillator from enering a stable state and that does not increase the fixed delays in the oscillator feedback paths. A sleep mode feature shuts down the oscillator to conserve power and capacitors are used to isolate the oscillator from high-frequency noise coupled through the power supply inputs.Type: GrantFiled: October 10, 1991Date of Patent: October 6, 1992Assignee: Samsung Semiconductor, Inc.Inventor: J. Eric Ruetz
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Patent number: 5153450Abstract: A programmable output driver circuit is provided having multiple drive capabilities for optimizing noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.Type: GrantFiled: July 16, 1991Date of Patent: October 6, 1992Assignee: Samsung Semiconductor, Inc.Inventor: J. Eric Ruetz