Abstract: Arrays of optical emitters, modulators, receivers and/or optoelectronic devices used in communication are printed with redundant elements to provide multiple solutions to select from at screening time to improve overall yield. Multiple optoelectronic devices are printed on common chiplets, tightly packed, or printed in sub-arrays.

Abstract: Mass-transfer printing an optical receiver element that also has part of the receiver front end integrated with the purpose of lowering the capacitance exposed to the sensitive input of the RX frontend. An optical receiver element with integrated front end where the silicon layer of the optical element is used to implement a silicon field-effect transistor process which is then used to incorporate the resistive transimpedance amplifier adjacent to the photodiode, resulting in a lower capacitance.

Abstract: Arrays of optical emitters, modulators, receivers and/or optoelectronic devices used in communication are printed with redundant elements to provide multiple solutions to select from at screening time to improve overall yield. Multiple optoelectronic devices are printed on common chiplets, tightly packed, or printed in sub-arrays.

Abstract: System architecture for devices with integrated electrical and optical power and signal distribution coupled with thermal dissipation. Systems include an electrical signal and electrical power delivery subsystem, an optical engine, an electrical interposer between the electrical signal and electrical power delivery subsystem and the optical engine, and an optical element to exchange optical signals with the optical engine and to exchange optical signals and optical power with an optical interface. Electrical signals and electrical power delivery from the electrical interposer to the optical engine and optical signal delivery from the optical element to the optical engine are provided through a common plane on the optical engine.

Abstract: A large-scale array of interleaved optoelectronic transmitters and receivers are integrated on the surface of a common substrate with integrated circuits. The interleaved configuration allows the optimization of a channel pair.