Patents by Inventor J K Ho

J K Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935789
    Abstract: A microelectronic device has a substrate attached to a substrate pad on a first face of the substrate, and a component attached to the substrate on the first face. The substrate has a component placement guide on the first face. The substrate has a singulation guide on a second face of the substrate, located opposite from the first face. The microelectronic device is formed by attaching the component to a substrate sheet which contains the substrate. The substrate sheet with the component is mounted on a singulation film so that the component contacts the singulation film. The singulation guide on the second face of the substrate is located opposite from the singulation film. The substrate is singulated from the substrate sheet. The substrate with the component is attached to the substrate pad on the first face of the substrate, adjacent to the component.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: March 19, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 11699649
    Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: July 11, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 11538740
    Abstract: A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jason Chien, Yuh-Harng Chien, J K Ho
  • Patent number: 11437303
    Abstract: A microelectronic device has a substrate attached to a substrate pad on a first face of the substrate, and a component attached to the substrate on the first face. The substrate has a component placement guide on the first face. The substrate has a singulation guide on a second face of the substrate, located opposite from the first face. The microelectronic device is formed by attaching the component to a substrate sheet which contains the substrate. The substrate sheet with the component is mounted on a singulation film so that the component contacts the singulation film. The singulation guide on the second face of the substrate is located opposite from the singulation film. The substrate is singulated from the substrate sheet. The substrate with the component is attached to the substrate pad on the first face of the substrate, adjacent to the component.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 6, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 11183450
    Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 11081429
    Abstract: A packaged semiconductor device includes a leadframe including a finger pad(s) that is integrated, and spans a finger pad area including a width narrower than its length. A first portion of the finger pad area provides a die support area. A second portion of the finger pad area provides a wire bond area including first and second wire bond pads on a first and second side of the die support area. One of the wire bond pads further includes a lead terminal integrally connected. The IC die has a top side with bond pads and a back side having a non-electrically conductive die attach material attached to the die support area. Bond wires extend from the bond pads to the first and second wire bond pads. A mold compound encapsulates the packaged semiconductor device leaving exposed at least the lead terminal on a bottom side of the packaged semiconductor device.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jason Chien, J K Ho, Yuh-Harng Chien
  • Publication number: 20210111103
    Abstract: A packaged semiconductor device includes a leadframe including a finger pad(s) that is integrated, and spans a finger pad area including a width narrower than its length. A first portion of the finger pad area provides a die support area. A second portion of the finger pad area provides a wire bond area including first and second wire bond pads on a first and second side of the die support area. One of the wire bond pads further includes a lead terminal integrally connected. The IC die has a top side with bond pads and a back side having a non-electrically conductive die attach material attached to the die support area. Bond wires extend from the bond pads to the first and second wire bond pads. A mold compound encapsulates the packaged semiconductor device leaving exposed at least the lead terminal on a bottom side of the packaged semiconductor device.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 15, 2021
    Inventors: Jason Chien, J K Ho, Yuh-Harng Chien
  • Publication number: 20210020549
    Abstract: A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Jason CHIEN, Yuh-Harng CHIEN, J K HO
  • Patent number: 10714418
    Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, J K Ho
  • Publication number: 20150108038
    Abstract: A new type of tape and reel tape based on the cover tape having projections extending from the bottom surface of the cover tape leaving a minimum of adhesive surface exposed to the surface mount die or packages contained in the pocket areas of the carrier tape.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Inventors: Randy Hsu, Shawn Wu, J K Ho, Debby Hsiao