Patents by Inventor J. Prakash Subramaniam Ganasan

J. Prakash Subramaniam Ganasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus of reducing transfer latency in an SOC interconnect
    Patent number: 7263566
    Abstract: Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: August 28, 2007
    Assignee: QUALCOMM Incorporated
    Inventors: J. Prakash Subramaniam Ganasan, Perry Willmann Remaklus, Jr.
  • Flow control method to improve bus utilization in a system-on-a-chip integrated circuit
    Patent number: 7246188
    Abstract: A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the requests. Slaves interconnected with the bus controller receive the requests for data and provide the requested data to the requesting masters. Control signals issued by the bus controller indicate to each slave which masters are not ready to receive the data it requested from that slave. The slaves delay transferring data to any masters that are not ready for the requested data, and provide data to different masters that are ready to receive the data they requested from the slaves.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: July 17, 2007
    Assignee: QUALCOMM Incorporated
    Inventors: J. Prakash Subramaniam Ganasan, Perry Willmann Remaklus, Jr.
  • Method and apparatus of reducing transfer latency in an SOC interconnect
    Publication number: 20060149874
    Abstract: Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: J. Prakash Subramaniam Ganasan, Perry Willmann Remaklus