Patents by Inventor Jérôme Lopez
Jérôme Lopez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240258184Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.Type: ApplicationFiled: April 9, 2024Publication date: August 1, 2024Applicant: STMicroelectronics (Grenoble 2) SASInventor: Jerome LOPEZ
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Patent number: 11984373Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.Type: GrantFiled: November 9, 2021Date of Patent: May 14, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Jerome Lopez
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Publication number: 20240087977Abstract: An integrated circuit includes an electronic chip having a face covered with a thermal interface material layer. A heat sink includes a mounting area fixed to the chip via the thermal interface material layer. The heat sink includes open notches extending into the mounting area to delimit fins separated from each other by the open notches.Type: ApplicationFiled: September 11, 2023Publication date: March 14, 2024Applicant: STMicroelectronics (Grenoble 2) SASInventors: Romain COFFY, Jerome LOPEZ
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Publication number: 20240072214Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
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Patent number: 11862757Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.Type: GrantFiled: September 24, 2021Date of Patent: January 2, 2024Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Olivier Zanellato, Remi Brechignac, Jerome Lopez
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Publication number: 20230411271Abstract: An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.Type: ApplicationFiled: June 9, 2023Publication date: December 21, 2023Applicant: STMicroelectronics (Grenoble 2) SASInventors: Luc PETIT, Jerome LOPEZ, Karine SAXOD
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Publication number: 20230290712Abstract: An interconnection substrate includes a thermomechanical support crossed by at least one electric interconnection hole. A first interconnection network is formed on a first surface of the thermomechanical support and a second interconnection network is formed on a second surface of the thermomechanical support. Each interconnection network includes and interconnection level formed by at least one metal track from which at least one metal via extends. The at least one metal track and the at least one metal via are embedded in an insulator layer so that the at least one metal via is flush with a surface of the insulator layer most distant from the thermomechanical support. At least one metal track protrudes from the insulator layer of the last interconnection level. The metal vias are configured to electrically couple together two adjacent levels and/or the last level with the at least one protruding metal track.Type: ApplicationFiled: March 7, 2023Publication date: September 14, 2023Applicant: STMicroelectronics (Grenoble 2) SASInventors: Fanny LAPORTE, Jerome LOPEZ
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Publication number: 20230121780Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: STMicroelectronics (Grenoble 2) SASInventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
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Patent number: 11557566Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: GrantFiled: March 31, 2020Date of Patent: January 17, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
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Publication number: 20220200117Abstract: A device for transmission of at least one high-frequency signal includes at least one first electrically-conductive track formed inside and/or on top of a flexible substrate.Type: ApplicationFiled: December 16, 2021Publication date: June 23, 2022Applicant: STMicroelectronics (Grenoble 2) SASInventors: Ludovic FOURNEAUD, Gregory BOUTELOUP, Jerome LOPEZ
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Publication number: 20220157679Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.Type: ApplicationFiled: November 9, 2021Publication date: May 19, 2022Applicant: STMicroelectronics (Grenoble 2) SASInventor: Jerome LOPEZ
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Publication number: 20220102591Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.Type: ApplicationFiled: September 24, 2021Publication date: March 31, 2022Applicant: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
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Patent number: 10892201Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.Type: GrantFiled: February 12, 2020Date of Patent: January 12, 2021Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) LtdInventors: Jerome Lopez, Roseanne Duca
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Publication number: 20200335466Abstract: A bumping matrix includes many bumps, wherein each bump is rotationally asymmetric in a plane of the bumping matrix. The bumps are orientated in a centripetal arrangement. Bumps in a first portion of the bumping matrix have a first pitch in a first axis and bumps in a second portion of the bumping matrix have a second pitch in the first axis. The second pitch is different from the first pitch. Bumps have an oblong shape with a longer diameter and a shorter diameter. The centripetal arrangement orients the longer diameter of the bumps is a direction radially extending from a center of the bumping matrix.Type: ApplicationFiled: April 14, 2020Publication date: October 22, 2020Applicants: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: Laurent SCHWARTZ, David KAIRE, Jerome LOPEZ
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Patent number: 10765412Abstract: The invention relates to an endoscopic instrument (1) having an elongate body with a distal end (4) designed to be introduced into the body of the patient so as to come into proximity with an internal organ, the distal end carrying a tool (7) for intervention on the internal organ. The endoscopic instrument has a fool (10) rigidly connected to the distal end and designed to bear on the internal organ, and also controllable means (13) for conferring movements on the tool, at least in directions transverse to a longitudinal axis (X) of the distal end of the endoscopic instrument, when the foot is bearing against the internal organ.Type: GrantFiled: June 25, 2012Date of Patent: September 8, 2020Assignees: UNIVERSITE PIERRE ET MARIE CURIE (PARIS 6), CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, MAUNA KEA TECHNOLOGIES, ENDOCONTROLInventors: Benoît Rosa, Benoît Herman, Jérôme Szewczyk, Guillaume Morel, Clément Vidal, Patrick Henri, François Lacombe, Jérôme Lopez
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Publication number: 20200227382Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: ApplicationFiled: March 31, 2020Publication date: July 16, 2020Applicant: STMicroelectronics (Grenoble 2) SASInventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
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Publication number: 20200185288Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.Type: ApplicationFiled: February 12, 2020Publication date: June 11, 2020Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) LtdInventors: Jerome LOPEZ, Roseanne DUCA
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Patent number: 10643970Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: GrantFiled: January 16, 2019Date of Patent: May 5, 2020Assignee: STMicroelectronics (Grenoble 2) SASInventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
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Patent number: 10600704Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.Type: GrantFiled: September 17, 2018Date of Patent: March 24, 2020Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) LtdInventors: Jerome Lopez, Roseanne Duca
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Publication number: 20190148334Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.Type: ApplicationFiled: January 16, 2019Publication date: May 16, 2019Applicant: STMicroelectronics (Grenoble 2) SASInventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ