Patents by Inventor Jérôme Lopez

Jérôme Lopez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240258184
    Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jerome LOPEZ
  • Patent number: 11984373
    Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: May 14, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jerome Lopez
  • Publication number: 20240087977
    Abstract: An integrated circuit includes an electronic chip having a face covered with a thermal interface material layer. A heat sink includes a mounting area fixed to the chip via the thermal interface material layer. The heat sink includes open notches extending into the mounting area to delimit fins separated from each other by the open notches.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 14, 2024
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Jerome LOPEZ
  • Publication number: 20240072214
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
  • Patent number: 11862757
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: January 2, 2024
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier Zanellato, Remi Brechignac, Jerome Lopez
  • Publication number: 20230411271
    Abstract: An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Luc PETIT, Jerome LOPEZ, Karine SAXOD
  • Publication number: 20230290712
    Abstract: An interconnection substrate includes a thermomechanical support crossed by at least one electric interconnection hole. A first interconnection network is formed on a first surface of the thermomechanical support and a second interconnection network is formed on a second surface of the thermomechanical support. Each interconnection network includes and interconnection level formed by at least one metal track from which at least one metal via extends. The at least one metal track and the at least one metal via are embedded in an insulator layer so that the at least one metal via is flush with a surface of the insulator layer most distant from the thermomechanical support. At least one metal track protrudes from the insulator layer of the last interconnection level. The metal vias are configured to electrically couple together two adjacent levels and/or the last level with the at least one protruding metal track.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 14, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Fanny LAPORTE, Jerome LOPEZ
  • Publication number: 20230121780
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
  • Patent number: 11557566
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 17, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
  • Publication number: 20220200117
    Abstract: A device for transmission of at least one high-frequency signal includes at least one first electrically-conductive track formed inside and/or on top of a flexible substrate.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Ludovic FOURNEAUD, Gregory BOUTELOUP, Jerome LOPEZ
  • Publication number: 20220157679
    Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 19, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jerome LOPEZ
  • Publication number: 20220102591
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 31, 2022
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
  • Patent number: 10892201
    Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 12, 2021
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) Ltd
    Inventors: Jerome Lopez, Roseanne Duca
  • Publication number: 20200335466
    Abstract: A bumping matrix includes many bumps, wherein each bump is rotationally asymmetric in a plane of the bumping matrix. The bumps are orientated in a centripetal arrangement. Bumps in a first portion of the bumping matrix have a first pitch in a first axis and bumps in a second portion of the bumping matrix have a second pitch in the first axis. The second pitch is different from the first pitch. Bumps have an oblong shape with a longer diameter and a shorter diameter. The centripetal arrangement orients the longer diameter of the bumps is a direction radially extending from a center of the bumping matrix.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 22, 2020
    Applicants: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Laurent SCHWARTZ, David KAIRE, Jerome LOPEZ
  • Patent number: 10765412
    Abstract: The invention relates to an endoscopic instrument (1) having an elongate body with a distal end (4) designed to be introduced into the body of the patient so as to come into proximity with an internal organ, the distal end carrying a tool (7) for intervention on the internal organ. The endoscopic instrument has a fool (10) rigidly connected to the distal end and designed to bear on the internal organ, and also controllable means (13) for conferring movements on the tool, at least in directions transverse to a longitudinal axis (X) of the distal end of the endoscopic instrument, when the foot is bearing against the internal organ.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: September 8, 2020
    Assignees: UNIVERSITE PIERRE ET MARIE CURIE (PARIS 6), CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, MAUNA KEA TECHNOLOGIES, ENDOCONTROL
    Inventors: Benoît Rosa, Benoît Herman, Jérôme Szewczyk, Guillaume Morel, Clément Vidal, Patrick Henri, François Lacombe, Jérôme Lopez
  • Publication number: 20200227382
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: March 31, 2020
    Publication date: July 16, 2020
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
  • Publication number: 20200185288
    Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) Ltd
    Inventors: Jerome LOPEZ, Roseanne DUCA
  • Patent number: 10643970
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 5, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
  • Patent number: 10600704
    Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: March 24, 2020
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) Ltd
    Inventors: Jerome Lopez, Roseanne Duca
  • Publication number: 20190148334
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ