Abstract: A multiplexing decoder/counter circuit for monitoring quadrature position encoders. The system includes an edge detector, a position counter, a position latch, a capture latch, and compare management means. Addressable memory blocks are used throughout the design. Information from external differential receivers is directed into a single quadrature decoder circuit using a switch with an effective 16 to 1 selection. An axis scanning state machine addresses multiple memory block based functions simultaneously. Scanning is performed in a circuitous manner in conjunction with the switch. The total circular loop frequency for the sequence is chosen to be equal to or greater than the maximum encoder frequency required. At each visitation of any particular memory address, the state of the circuit is reestablished from the last visit by the scanning state machine. Any change in quadrature signals is noted, and any up or down count is accumulated to the position counter.

Abstract: A wafer sorting system utilizing optical character recognition and optical "gate sensors" to determine the orientation of the wafers for prealigning. It is envisioned that the machine will be installed in conjunction with a computer controller and multiple cassette stations. A first end of a transfer arm of a robot is equipped with an end effector to transfer individual wafers. The end effector of the transfer arm is extendable and retractable to select and remove the desired wafer from its cassette, and to transfer it to the prealigner or a target cassette in its proper orientation. The end effector includes a vacuum pickup and a sensor that enables detection of presence or absence of wafers in the cassette, and any misaligned wafers in the cassette. Further gate sensors are mounted on the prealigner to accomplish the orientation function prior to the wafer being placed on the prealigner chuck. Multiple perimeter points are used to determine the position of the center of the wafer.

Abstract: A multiplexing circuit which rapidly shares a single rate generator among up to 16 different motors. The circuit utilizes an addend memory block with n-bit by m-deep memory structures. Each memory address represents a particular stepper motor in the system. An axis scanning state machine 9 drives the memory structure address lines in a circuitous manner. At each memory address visit, the state of the circuit is re-established based on information stored from the last visit. The addition operation is performed to change the accumulator value in memory block 102. Any possible edge event is noted by edge detector 11. An edge produces a step and position monitor count. The axis-scanning state machine then moves on to the next address representing the next motor. The axis-scanning memory address influences memory structures throughout the device including accumulator value in memory block 102, addend memory values 12, device configuration 13, and step monitor counter 14.

Abstract: A computer program that evaluates data to determine the position of the center of a wafer. The program processes data generated by gate sensors that detect points on the wafer's outer edge. The sensors provide information about a leading and a trailing edge of the wafer. The program then determines if the data points are those on the circular perimeter of the wafer so that points on the flat or notch may be eliminated from the calculation of the center point.