Patents by Inventor Jörg Lindner

Jörg Lindner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160130160
    Abstract: The present invention relates to a process for reducing the total organic carbon (TOC) in an aqueous mixture M1 obtained as wastewater from a process for the preparation of an olefin oxide, the process for reducing the TOC comprising: (a) contacting the mixture M1 which contains at least one oxygenate having from 1 to 16 carbon atoms with an adsorbing agent and adsorbing at least a portion of an oxygenate at the adsorbing agent; (b) separating an aqueous mixture M2 from the adsorbing agent, the mixture M2 being depleted of the oxygenate adsorbed in (a); and (c) separating an oxygenate from the mixture M2 obtained in (b) by subjecting the mixture M2 to reverse osmosis in at least one reverse osmosis unit containing a reverse osmosis membrane obtaining an aqueous mixture M3 being depleted of this oxygenate.
    Type: Application
    Filed: June 4, 2014
    Publication date: May 12, 2016
    Applicants: BASF SE, Dow Global Technologies LLC
    Inventors: Holger BAER, Harlan R. GOLTZ, Joerg LINDNER, Astrid LENZ
  • Patent number: 8829532
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: September 9, 2014
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Maik Häberlen, Jörg Lindner, Bernd Stritzker
  • Patent number: 8383495
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: February 26, 2013
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Maik Haeberlen, Joerg Lindner, Bernd Stritzker
  • Publication number: 20110151650
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Application
    Filed: March 2, 2011
    Publication date: June 23, 2011
    Applicant: SILTRONIC AG
    Inventors: Brian Murphy, Maik Häberlen, Jörg Lindner, Bernd Stritzker
  • Patent number: 7294564
    Abstract: The following invention provides a method for forming a layered semiconductor structure having a layer of a first semiconductor material on a substrate of at least one second semiconductor material, comprising the steps of: providing said substrate; burying said layer of said first semiconductor material in said substrate, said buried layer having an upper surface and a lower surface and dividing said substrate into an upper part and a lower part; creating a buried damage layer; which at least partly adjoins and/or partly includes said upper surface of said buried layer; and removing said upper part of said substrate and said buried damage layer for exposing said buried layer. The invention also provides a corresponding layered semiconductor structure.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: November 13, 2007
    Assignee: Siltronic AG
    Inventors: Wilfried Attenberger, Jörg Lindner, Bernd Stritzker
  • Publication number: 20060267024
    Abstract: The invention relates to a semiconductor layer structure of a monocrystalline silicon carbide layer on a ?150 mm diameter silicon wafer, the silicon carbide layer having a surface roughness of at most 0.5 nm RMS and a micropipe density of at most 1 cm?2 and being free of defects produced during crystal growth or epitaxial deposition, and to a process for producing such a semiconductor layer structure, by implanting carbon ions into a silicon wafer, heat treating the silicon wafer to produce a buried monocrystalline silicon carbide layer and flanking noncrystalline transition regions, followed by removing the upper silicon layer and noncrystalline transition region above the monocrystalline silicon carbide layer, thus uncovering the monocrystalline silicon carbide layer, and chemical mechanical planarizing the monocrystalline silicon carbide layer to a surface roughness of less than 0.5 nm RMS.
    Type: Application
    Filed: May 22, 2006
    Publication date: November 30, 2006
    Applicant: Siltronic AG
    Inventors: Brian Murphy, Maik Haeberlen, Joerg Lindner
  • Patent number: 6323350
    Abstract: The present invention relates to a liquid phase process for preparing an olefin oxide from an olefin in a cascade of two or more reactors, in a baffled tank reactor or in a plug flow reactor which process comprises the steps of a) contacting the olefin in a solvent with oxygen or an oxygen-containing gas in a first reactor of the reactor cascade or in a first stage of the baffled tank reactor or of the plug flow reactor, thereby producing a mixture comprising olefin oxide, non-converted olefin, solvent and by-products and b) transferring at least a portion of the mixture obtained in step a) to a second reactor of the reactor cascade or to a second stage of the baffled tank reactor or plug flow reactor, adding an additional amount of i) oxygen or an oxygen-containing gas and/or ii) olefin to the mixture and continuing the reaction.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: November 27, 2001
    Assignee: The Dow Chemical Company
    Inventors: Joerg Lindner, Wolfgang Taeuber, Hans-Juergen Wertgen