Patents by Inventor Jörg Ortner

Jörg Ortner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908763
    Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: February 20, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Prashanth Makaram, John Cooper, Joerg Ortner, Stephan Pindl, Caterina Travan, Alexander Zoepfl
  • Publication number: 20230282596
    Abstract: In an embodiment, a semiconductor wafer includes a front surface, a plurality of active component positions, and at least one composite alignment mark arranged on the front surface and indicating a unique orientation of the semiconductor wafer. The composite alignment mark includes a first portion that has at least one raised section formed of a first material and a second portion that is positioned laterally adjacent the first portion. The second portion has at least one raised section formed of a second material that is different form the first material.
    Type: Application
    Filed: February 1, 2023
    Publication date: September 7, 2023
    Inventors: Andreas Kleinbichler, Daniel Maurer, Joerg Ortner, Rudolf Rothmaler
  • Publication number: 20230275033
    Abstract: A semiconductor substrate includes a semiconductor base substrate. An alignment structure is formed on a surface of the semiconductor base substrate. An epitaxial layer is deposited on the surface of the semiconductor base substrate. The alignment structure includes an area of the surface of the semiconductor base substrate that is formed as a groove pattern. Grooves of the groove pattern are aligned with a specific crystallographic direction of the semiconductor base substrate. The specific crystallographic direction provides for a slower epitaxial growth rate on such a groove-patterned base substrate surface area compared to epitaxial growth on a surface of the semiconductor base substrate adjacent to the groove-patterned area.
    Type: Application
    Filed: February 14, 2023
    Publication date: August 31, 2023
    Inventors: Thomas Huber, Matthias Kuenle, Iris Moder, Joerg Ortner
  • Patent number: 11640908
    Abstract: A method of implanting an implant species into a substrate at different depths is described. The method includes forming an implant mask over the substrate. The implant mask includes a first implant zone designed as an opening and a second implant zone designed as a block array. The implant species is implanted through the implant mask under an implant angle tilted against a block plane, such that a first implant area is formed by the implant species at a first depth in the substrate beneath the first implant zone and a second implant area is formed by the implant species at a second depth in the substrate beneath the second implant zone. The first depth is greater than the second depth.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 2, 2023
    Assignee: Infineon Technologies AG
    Inventors: Joerg Ortner, Marcel Heller, Dieter Kaiser, Nicolo Morgana, Jens Schneider
  • Publication number: 20220013424
    Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Prashanth Makaram, John Cooper, Joerg Ortner, Stephan Pindl, Caterina Travan, Alexander Zoepfl
  • Patent number: 11189539
    Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 30, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Prashanth Makaram, John Cooper, Joerg Ortner, Stephan Pindl, Caterina Travan, Alexander Zoepfl
  • Publication number: 20200373163
    Abstract: A method of implanting an implant species into a substrate at different depths is described. The method includes forming an implant mask over the substrate. The implant mask includes a first implant zone designed as an opening and a second implant zone designed as a block array. The implant species is implanted through the implant mask under an implant angle tilted against a block plane, such that a first implant area is formed by the implant species at a first depth in the substrate beneath the first implant zone and a second implant area is formed by the implant species at a second depth in the substrate beneath the second implant zone. The first depth is greater than the second depth.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 26, 2020
    Inventors: Joerg Ortner, Marcel Heller, Dieter Kaiser, Nicolo Morgana, Jens Schneider
  • Patent number: 10802404
    Abstract: An exposure method includes projecting a reticle pattern into a first exposure field of a photoresist layer, wherein the reticle pattern includes first and second line patterns on opposite edges of the reticle pattern and wherein at least the first line pattern includes an end section through which light flux decreases outwards. The reticle pattern is further projected into a second exposure field of the photoresist layer, wherein a first tapering projection zone of the end section of the first line pattern in the second exposure field overlaps a projection area of the second line pattern in the first exposure field.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 13, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Joerg Ortner, Iris Moder, Ingo Muri
  • Publication number: 20190378776
    Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 12, 2019
    Inventors: Prashanth Makaram, John Cooper, Joerg Ortner, Stephan Pindl, Caterina Travan, Alexander Zoepfl
  • Publication number: 20180267408
    Abstract: An exposure method includes projecting a reticle pattern into a first exposure field of a photoresist layer, wherein the reticle pattern includes first and second line patterns on opposite edges of the reticle pattern and wherein at least the first line pattern includes an end section through which light flux decreases outwards. The reticle pattern is further projected into a second exposure field of the photoresist layer, wherein a first tapering projection zone of the end section of the first line pattern in the second exposure field overlaps a projection area of the second line pattern in the first exposure field.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 20, 2018
    Inventors: Joerg Ortner, Iris Moder, Ingo Muri
  • Publication number: 20170309565
    Abstract: A method for use in manufacturing semiconductor devices includes providing a structured layer on a wafer, and selectively providing a substance on a selected portion of the structured layer. A die comprises a semiconductor device on a substrate, where the semiconductor device includes a substance, and where the substance has a sidewall that is sheer with respect to one or more of a base surface or a top surface of the substrate.
    Type: Application
    Filed: April 25, 2016
    Publication date: October 26, 2017
    Applicant: Infineon Technologies AG
    Inventors: Joerg Ortner, John Cooper
  • Patent number: 9704748
    Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: July 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joerg Ortner, Michael Roesner, Gudrun Stranzl, Rudolf Rothmaler
  • Publication number: 20160379884
    Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Joerg Ortner, Michael Roesner, Gudrun Stranzl, Rudolf Rothmaler
  • Patent number: 9496339
    Abstract: A semiconductor device includes a central portion and an edge termination portion outside the central portion. The central portion includes a transistor cell array in a semiconductor substrate. Components of transistor cells of the transistor cell array are disposed in adjacent trench structures in the semiconductor substrate. The trench structures run in a first linear direction parallel to a main surface of the semiconductor substrate. The trench structures include a plurality of concatenated trench segments in a plane parallel to the main surface in the central portion, at least one of the trench segments connecting a first point and a second point of one trench structure, the first point and the second point being arranged along the first linear direction. The trench segment comprises a portion extending in a direction different from the first direction.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Minghao Jin, Rudolf Rothmaler, Oliver Blank, Joerg Ortner
  • Patent number: 9339868
    Abstract: In a method of processing a substrate in accordance with an embodiment, a trench may be formed in the substrate, a stamp device may be disposed at least in the trench; at least one part of the trench that is free from the stamp device may be at least partially filled with trench filling material; and the stamp device may be removed from the trench.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: May 17, 2016
    Assignee: Infineon Technologies AG
    Inventors: Joerg Ortner, Michael Sorger
  • Publication number: 20150349056
    Abstract: A semiconductor device includes a central portion and an edge termination portion outside the central portion. The central portion includes a transistor cell array in a semiconductor substrate. Components of transistor cells of the transistor cell array are disposed in adjacent trench structures in the semiconductor substrate. The trench structures run in a first linear direction parallel to a main surface of the semiconductor substrate. The trench structures include a plurality of concatenated trench segments in a plane parallel to the main surface in the central portion, at least one of the trench segments connecting a first point and a second point of one trench structure, the first point and the second point being arranged along the first linear direction. The trench segment comprises a portion extending in a direction different from the first direction.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 3, 2015
    Inventors: Minghao Jin, Rudolf Rothmaler, Oliver Blank, Joerg Ortner
  • Patent number: 9171806
    Abstract: A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: October 27, 2015
    Assignee: Infineon Technologies AG
    Inventor: Joerg Ortner
  • Patent number: 9165889
    Abstract: An alignment mark definer is configured to provide a geometrical definition for an actual alignment structure to be formed at a temporary surface of a substrate based on a desired appearance of the alignment mark and on an expected alteration of an appearance of the actual alignment structure caused by a deposition material deposited on the temporary surface and the actual alignment structure.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 20, 2015
    Assignee: Infineon Technologies AG
    Inventors: Joerg Ortner, Josef Campidell, Andreas Greiner
  • Patent number: 9142444
    Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 22, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zundel, Erwin Bacher, Andreas Behrendt, Joerg Ortner, Walter Rieger, Rudolf Zelsacher
  • Patent number: 9126260
    Abstract: In a method of processing a substrate in accordance with an embodiment, a trench may be formed in the substrate, imprint material may be deposited at least into the trench, the imprint material in the trench may be embossed using a stamp device, and the stamp device may be removed from the trench.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: September 8, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Joerg Ortner, Michael Sorger