Abstract: A control pulse generator for the cyclical fault-free generation of an accurate sequence of control pulses utilizing a quartz pulse generator which is operatively connected to and adapted to initiate actuation of a plurality of serially connected to delay members over a control circuit which is operative, at the termination of a cycle of actuation of the serially connected delay members, to limit the initiation of a succeeding cycle by a pulse from the generator to a predetermined period of time following termination of the first cycle of operation and functioning as a self-holding circuit when the period duration of the quartz generator signals coincide with the running time of the serially connected delay members. Further means are provided for checking the duration of the limiting period to insure proper operation.

Abstract: A comparator circuit for two multi-digit binary codes, particularly binary numbers, in which a series circuit is formed by n number of majority decision elements connected in series, each of which has three inputs, the characteristic information of the first binary number being supplied to a respective input in a negated manner, and the information of the second binary number to another respective input in a non-negated manner. In one embodiment, an evaluation circuit for a qualitative comparison result utilizes a test pulse in conjunction with the binary numbers, which pulse is supplied to the last element of the series connected elements. Depending on the embodiment, the qualitative comparision result may be read out either in response to a test pulse or continuously.

Abstract: A counting element for constructing synchronous modulo-n or modulo-2.sup.m counters having a storage member which comprises a master-slave flip-flop. A majority decision circuit is connected to the master-slave flip-flop to provide a majority decision indication concerning two variables and an output of the slave, the slave being directly connected at one input thereof with the master and indirectly by way of an inverter at its other input so that the storage member fulfills the truth tableS R Qto Qtl ______________________________________ L O O O L L O L O L L L O O L O L O L L L L L L O L O O O O O O ______________________________________which satisfies the Boolean equationQt1 = S .sup.. R + Qto .sup.. (S + R).A plurality of counter elements are connected in a serial chain, and connected with additional majority decision circuits, and other components such as additional storage circuits and EXCLUSIVE OR gates, to constitute either modulo-n or modulo-.sup.m counters.

Abstract: A synchronous shift register has serial and parallel data inputs and a basic position input. The individual stages of the shift register are each constructed with a master-slave flip-flop which is fed back by way of a majority decision element. To the set and reset inputs of the storage elements an additional majority decision circuit is connected by which the stages are connected in series and over which the input and output, respectively, of data takes place. The synchronous shift register requires little construction effort and serves as a safety circuit system. In a safety circuit system dual channel processing is provided. If the processing takes place accurately, out of phase (anti-phase) signals appear in the channels.

Abstract: A ring counter has a plurality of synchronously controlled counting flip-flops. Each of the flip-flops are constructed as a masterslave flip-flop with a majority decision input circuit with three input variables. An even number of the counting flip-flops, which operate in accordance with the Boolean equation Qtl = S . R + Qto . (S + R) are ring connected by way of their set inputs and the outputs associated with the set inputs. The reset inputs of the counting flip-flops of an even order, and of an uneven order, are connected with first and second control lines, respectively, for receiving counting information and negated counting information, respectively. The counting information for the first counting flip-flop is supplied and emitted with inversion.