Patents by Inventor J. Robert Reid

J. Robert Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated chip scale packages
    Patent number: 10553511
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: February 4, 2020
    Assignee: CUBIC CORPORATION
    Inventor: J. Robert Reid
  • SUBSTRATE-FREE INTERCONNECTED ELECTRONIC MECHANICAL STRUCTURAL SYSTEMS
    Publication number: 20200022277
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components.
    Type: Application
    Filed: March 28, 2019
    Publication date: January 16, 2020
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • STRUCTURES AND METHODS FOR INTERCONNECTS AND ASSOCIATED ALIGNMENT AND ASSEMBLY MECHANISMS FOR AND BETWEEN CHIPS, COMPONENTS, AND 3D SYSTEMS
    Publication number: 20190393580
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Application
    Filed: January 25, 2019
    Publication date: December 26, 2019
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • INTEGRATED CHIP SCALE PACKAGES
    Publication number: 20190287869
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventor: J. Robert Reid
  • Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems
    Patent number: 10361471
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: July 23, 2019
    Assignee: NUVOTRONICS, INC
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • Integrated chip scale packages
    Patent number: 10319654
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 11, 2019
    Assignee: CUBIC CORPORATION
    Inventor: J. Robert Reid
  • INTEGRATED CHIP SCALE PACKAGES
    Publication number: 20190172764
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Inventor: J. Robert Reid
  • Substrate-free interconnected electronic mechanical structural systems
    Patent number: 10257951
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 9, 2019
    Assignee: NUVOTRONICS, INC
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems
    Patent number: 10193203
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: January 29, 2019
    Assignee: NUVOTRONICS, INC
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • SUBSTRATE-FREE INTERCONNECTED ELECTRONIC MECHANICAL STRUCTURAL SYSTEMS
    Publication number: 20180153055
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 31, 2018
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • STRUCTURES AND METHODS FOR INTERCONNECTS AND ASSOCIATED ALIGNMENT AND ASSEMBLY MECHANISMS FOR AND BETWEEN CHIPS, COMPONENTS, AND 3D SYSTEMS
    Publication number: 20180123217
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 3, 2018
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • Substrate-free interconnected electronic mechanical structural systems
    Patent number: 9888600
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components are provided.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 6, 2018
    Assignee: NUVOTRONICS, INC
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • Stacked, switched filter banks
    Patent number: 9660614
    Abstract: Switched filter banks realized in a stacked arrangement.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: May 23, 2017
    Assignee: NUVOTRONICS, INC.
    Inventor: J. Robert Reid
  • STACKED, SWITCHED FILTER BANKS
    Publication number: 20170033773
    Abstract: Switched filter banks realized in a stacked arrangement.
    Type: Application
    Filed: July 25, 2016
    Publication date: February 2, 2017
    Inventor: J. Robert Reid
  • STRUCTURES AND METHODS FOR INTERCONNECTS AND ASSOCIATED ALIGNMENT AND ASSEMBLY MECHANISMS FOR AND BETWEEN CHIPS, COMPONENTS, AND 3D SYSTEMS
    Publication number: 20160294035
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Application
    Filed: March 18, 2016
    Publication date: October 6, 2016
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • SUBSTRATE-FREE INTERCONNECTED ELECTRONIC MECHANICAL STRUCTURAL SYSTEMS
    Publication number: 20160198584
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components are provided.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • Substrate-free mechanical interconnection of electronic sub-systems using a spring configuration
    Patent number: 9306254
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components are provided.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 5, 2016
    Assignee: NUVOTRONICS, INC.
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • Microstructure including microstructural waveguide elements and/or IC chips that are mechanically interconnected to each other
    Patent number: 9306255
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 5, 2016
    Assignee: NUVOTRONICS, INC.
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • Millimeter Wave Filter for Wireless Communications Systems
    Publication number: 20120256708
    Abstract: A millimeter wave transmission line filter having a plurality of filter pole determining coupled cavities fabricated with a multiple lithographic layer micro-machining process. The filter cavities are oriented perpendicular to an underlying substrate element in order to achieve micromachining, fabrication and accuracy advantages. Multiple filters can be used in a frequency multiplex arrangement as in a duplexer. Radio frequencies in the 15 to 300 gigahertz range are contemplated.
    Type: Application
    Filed: June 25, 2012
    Publication date: October 11, 2012
    Applicant: Government of the United States, as represented by the Secretary of the Air Force
    Inventor: J. Robert Reid, JR.
  • Method of making a millimeter wave transmission line filter
    Patent number: 8230564
    Abstract: A millimeter wave transmission line filter having a plurality of filter pole determining coupled cavities fabricated with a multiple lithographic layer micromachining process. The filter cavities are oriented perpendicular to an underlying substrate element in order to achieve micromachining, fabrication and accuracy advantages. Multiple filters can be used in a frequency multiplex arrangement as in a duplexer. Radio frequencies in the 15 to 300 gigahertz range are contemplated.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 31, 2012
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: J. Robert Reid, Jr.