Patents by Inventor Ja-Rong Hsieh

Ja-Rong Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Addition of planarizing dielectric layer to reduce a dishing phenomena experienced during a chemical mechanical procedure used in the formation of shallow trench isolation regions
    Patent number: 6399461
    Abstract: A process for fabricating silicon oxide filled, shallow trench isolation (STI), regions, in a semiconductor substrate, featuring the use of a disposable boro-phosphosilicate glass (BPSG), layer, used for planarization of various width, silicon oxide filled, STI regions, has been developed. After completely filling all STI shapes with a high density plasma (HDP), silicon oxide layer, resulting in a non-planar, HDP silicon oxide top surface topography, a BPSG layer is deposited. An anneal procedure is then performed resulting in a planar top surface topography of the reflowed BPSG layer. A chemical mechanical polishing procedure is next employed to remove the planar, reflowed BPSG layer, and portions of the underlying HDP silicon oxide, from the top surface of a silicon nitride stop layer, resulting in a planar top surface topography for all silicon oxide filled, insulator regions.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: June 4, 2002
    Assignee: Promos Technologies, Inc.
    Inventors: Pao-Kuo Liu, Ja-Rong Hsieh, Zhi-Yong Wang