Patents by Inventor Jack A. Allan

Jack A. Allan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION USING A CONDUCTIVE REGION
    Publication number: 20080268610
    Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.
    Type: Application
    Filed: July 9, 2008
    Publication date: October 30, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, David Vaclav Horak, Charles William Koburger, Jack Allan Mandelman, William Robert Tonti
  • Hybrid Substrates and Methods for Forming Such Hybrid Substrates
    Publication number: 20080258181
    Abstract: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.
    Type: Application
    Filed: April 20, 2007
    Publication date: October 23, 2008
    Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, John Gerard Gaudiello, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, Jack Allan Mandelman, William Robert Tonti
  • Design Structure Incorporating a Hybrid Substrate
    Publication number: 20080258222
    Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.
    Type: Application
    Filed: October 24, 2007
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, John Gerard Gaudiello, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, Jack Allan Mandelman, William Robert Tonti
  • STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES FOR USE IN SRAM DEVICES
    Publication number: 20080251878
    Abstract: Device structures embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes static random access memory (SRAM) devices. The design structure includes a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The design structure further comprises an electrically connective bridge extending across the first semiconductor region. A portion of the electrically connective bridge electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure.
    Type: Application
    Filed: October 22, 2007
    Publication date: October 16, 2008
    Applicant: International Business Machines Corporation
    Inventors: Jack Allan Mandelman, Haining Yang
  • Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices
    Publication number: 20080251934
    Abstract: Semiconductor device structures and methods of fabricating such semiconductor device structures for use in static random access memory (SRAM) devices. The semiconductor device structure comprises a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The device structure further comprises an electrically connective bridge extending across the first semiconductor region. The electrically connective bridge has a portion that electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure.
    Type: Application
    Filed: April 13, 2007
    Publication date: October 16, 2008
    Inventors: Jack Allan Mandelman, Haining Yang
  • METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED SUSCEPTIBILITY TO LATCH-UP AND SEMICONDUCTOR DEVICE STRUCTURES FORMED BY THE METHODS
    Publication number: 20080242016
    Abstract: Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.
    Type: Application
    Filed: May 8, 2008
    Publication date: October 2, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, Jimmy Konstantinos Kontos, Jack Allan Mandelman, William Robert Tonti
  • BULK FinFET DEVICE
    Publication number: 20080233699
    Abstract: A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
    Type: Application
    Filed: June 5, 2008
    Publication date: September 25, 2008
    Inventors: Roger Allen Booth, William Paul Hovis, Jack Allan Mandelman
  • APPARATUS FOR IMPLEMENTING ENHANCED HAND SHAKE PROTOCOL IN MICROELECTRONIC COMMUNICATION SYSTEMS
    Publication number: 20080227425
    Abstract: A method and apparatus are provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the transmitter terminates communications, drops the common mode level with the idle input being activated.
    Type: Application
    Filed: May 27, 2008
    Publication date: September 18, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, James Stephen Mason
  • SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES
    Publication number: 20080224175
    Abstract: Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further includes a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
    Type: Application
    Filed: May 30, 2008
    Publication date: September 18, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman
  • Fuse/anti-fuse structure and methods of making and programming same
    Publication number: 20080224261
    Abstract: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor stricture Methods of making and programming the fuse/anti-fuse structures are also provided.
    Type: Application
    Filed: May 27, 2008
    Publication date: September 18, 2008
    Applicant: International Business Machines Corporation
    Inventors: Louis C. Hsu, Rajiv V. Joshi, Jack Allan Mandelman, Chih-Chao Yang
  • METHODS AND SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION USING A CONDUCTIVE REGION
    Publication number: 20080217698
    Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.
    Type: Application
    Filed: May 22, 2008
    Publication date: September 11, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, David Vaclav Horak, Charles William Koburger, Jack Allan Mandelman, William Robert Tonti
  • METHODS FOR FORMING SEMICONDUCTOR STRUCTURES WITH BURIED ISOLATION COLLARS AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS
    Publication number: 20080220586
    Abstract: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.
    Type: Application
    Filed: May 22, 2008
    Publication date: September 11, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Jack Allan Mandelman
  • Latch-Up Resistant Semiconductor Structures on Hybrid Substrates and Methods for Forming Such Semiconductor Structures
    Publication number: 20080217690
    Abstract: Latch-up resistant semiconductor structures formed on a hybrid substrate and methods of forming such latch-up resistant semiconductor structures. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.
    Type: Application
    Filed: February 28, 2007
    Publication date: September 11, 2008
    Inventors: Jack Allan Mandelman, William Robert Tonti
  • SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES
    Publication number: 20080220583
    Abstract: Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
    Type: Application
    Filed: May 22, 2008
    Publication date: September 11, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman
  • METHODS FOR FORMING SEMICONDUCTOR STRUCTURES WITH BURIED ISOLATION COLLARS AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS
    Publication number: 20080217671
    Abstract: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.
    Type: Application
    Filed: May 22, 2008
    Publication date: September 11, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Jack Allan Mandelman
  • METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS
    Publication number: 20080211054
    Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
    Type: Application
    Filed: May 14, 2008
    Publication date: September 4, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Brian Joseph Greene, Jack Allan Mandelman
  • ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS
    Publication number: 20080206978
    Abstract: A structure fabrication method. The method includes providing a structure. The structure includes (a) a substrate layer, (b) a first fuse electrode in the substrate layer, and (c) a fuse dielectric layer on the substrate layer and the first fuse electrode. The method further includes (i) forming an opening in the fuse dielectric layer such that the first fuse electrode is exposed to a surrounding ambient through the opening, (ii) forming a fuse region on side walls and bottom walls of the opening such that the fuse region is electrically coupled to the first fuse electrode, and (iii) after said forming the fuse region, filling the opening with a dielectric material.
    Type: Application
    Filed: February 28, 2007
    Publication date: August 28, 2008
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, William Robert Tonti, Chih-Chao Yang
  • METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED SUSCEPTIBILITY TO LATCH-UP AND SEMICONDUCTOR DEVICE STRUCTURES FORMED BY THE METHODS
    Publication number: 20080203492
    Abstract: Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.
    Type: Application
    Filed: May 8, 2008
    Publication date: August 28, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, Jimmy Konstantinos Kontos, Jack Allan Mandelman, William Robert Tonti
  • Structure Incorporating Latch-Up Resistant Semiconductor Device Structures on Hybrid Substrates
    Publication number: 20080203522
    Abstract: Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.
    Type: Application
    Filed: October 22, 2007
    Publication date: August 28, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack Allan Mandelman, William Robert Tonti
  • FinFET with Reduced Gate to Fin Overlay Sensitivity
    Publication number: 20080203468
    Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.
    Type: Application
    Filed: February 28, 2007
    Publication date: August 28, 2008
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman, John Edward Sheets