Patents by Inventor Jack Ajoian

Jack Ajoian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180063951
    Abstract: A process for forming an encapsulating mold compound into a molded solder mask on a bottom surface of a PCB is provided that allows the molded solder mask to have a very precise, preselected thickness, or height, while also ensuring that no gaps between the solder mask and side walls of the electrical contact pads exist. A circuit board and circuit board assembly that incorporate the molded solder mask are also provided. The molded solder mask is fabricated in such a way that overlap between the molded solder mask and the electrical contact pads and gaps between the molded solder mask and the side walls of the electrical contact pads are avoided. In addition, the molded solder mask allows the pitch between adjacent electrical contact pads to be greatly reduced compared to the pitch that is possible using a traditional solder mask formed by the traditional photolithographic approach.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Nitesh Kumbhat, Li Sun, Aaron Lee, Deog-Soon Choi, Hyun-Mo Ku, Jack Ajoian
  • Patent number: 9907169
    Abstract: A process for forming an encapsulating mold compound into a molded solder mask on a bottom surface of a PCB is provided that allows the molded solder mask to have a very precise, preselected thickness, or height, while also ensuring that no gaps between the solder mask and side walls of the electrical contact pads exist. A circuit board and circuit board assembly that incorporate the molded solder mask are also provided. The molded solder mask is fabricated in such a way that overlap between the molded solder mask and the electrical contact pads and gaps between the molded solder mask and the side walls of the electrical contact pads are avoided. In addition, the molded solder mask allows the pitch between adjacent electrical contact pads to be greatly reduced compared to the pitch that is possible using a traditional solder mask formed by the traditional photolithographic approach.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 27, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nitesh Kumbhat, Li Sun, Aaron Lee, Deog-Soon Choi, Hyun-Mo Ku, Jack Ajoian
  • Patent number: 9832865
    Abstract: A build-up process for fabricating a multi-layer PCB is provided during which a mezzanine redistribution, or routing, structure is formed within one of the PCB dielectric material layers that allows additional electrical interconnections (i.e., traces and crossovers) to be made within that layer, thereby obviating the need to add an additional PCB layer in order to make those interconnections. The mezzanine redistribution structure also can be interconnected with the metal layers that are above and below it to further increase routing complexity and flexibility. The mezzanine redistribution structure can be formed without increasing the total thickness of the PCB and without substantially increasing costs.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: November 28, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Jack Ajoian, Padam Jain
  • Publication number: 20170311444
    Abstract: A build-up process for fabricating a multi-layer PCB is provided during which a mezzanine redistribution, or routing, structure is formed within one of the PCB dielectric material layers that allows additional electrical interconnections (i.e., traces and crossovers) to be made within that layer, thereby obviating the need to add an additional PCB layer in order to make those interconnections. The mezzanine redistribution structure also can be interconnected with the metal layers that are above and below it to further increase routing complexity and flexibility. The mezzanine redistribution structure can be formed without increasing the total thickness of the PCB and without substantially increasing costs.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Inventors: Jack Ajoian, Padam Jain
  • Patent number: 9668340
    Abstract: A build-up process for fabricating a multi-layer PCB is provided that prevents, or at least reduces the lengths of, overhangs in the finishing metal layer that is plated onto the electrical contact metal layer. The metal seed layer is etched away prior to plating the finishing metal layer onto the electrical contact metal layer. The electrical contact metal layer is covered with a layer of dielectric material, which is then patterned to selectively expose preselected areas of the electrical contact metal layer. The exposed preselected areas of the electrical contact metal layer are then plated with the finishing layer of metal. The result is that overhangs are eliminated or at least greatly reduced in length. In addition, the dielectric material layer serves a function similar to that of a solder mask and obviates the need to apply the oxide to serve as a solder mask.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 30, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jack Ajoian, Lea-Teng Lee
  • Publication number: 20160064252
    Abstract: An electronic module includes a substrate, conductive pads at top and bottom surfaces of the substrate, at least one electronic component disposed on the top surface of the substrate and soldered to the pads at the top surface of the substrate, a molding compound covering the at least one electronic component, and a solder resist comprising an organo-metallic compound at regions between respective ones of the pads at the bottom surface of the substrate. The module is manufactured using both an OSP surface finishing process to coat the pads at the top surface of the substrate with OSP so as to protect the pads from oxidation while the electronic component is being connected to the substrate, and an oxide surface finish process to form the solder resist.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventor: Jack Ajoian
  • Patent number: 9085826
    Abstract: A method is provided for fabricating a substrate having multiple metal layers separated by one or more dielectric layers, respectively. The method includes forming a cavity in at least one dielectric layer through an exposed portion of a top dielectric layer of the substrate, applying metal to side and bottom surfaces of the cavity, forming a pattern through a portion of the metal applied to the bottom surface of the cavity, and micro-etching the metal applied to the bottom surface of the cavity. The micro-etching extends the pattern through a remaining portion of the metal applied to the bottom surface of the cavity.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 21, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Jack Ajoian
  • Publication number: 20150090688
    Abstract: A method is provided for fabricating a substrate having multiple metal layers separated by one or more dielectric layers, respectively. The method includes forming a cavity in at least one dielectric layer through an exposed portion of a top dielectric layer of the substrate, applying metal to side and bottom surfaces of the cavity, forming a pattern through a portion of the metal applied to the bottom surface of the cavity, and micro-etching the metal applied to the bottom surface of the cavity. The micro-etching extends the pattern through a remaining portion of the metal applied to the bottom surface of the cavity.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventor: Jack Ajoian