Patents by Inventor Jack C. Lee
Jack C. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210408372Abstract: The present disclosure provides a 2-dimensional (2D) non-volatile switch (2DNS), with a vertical metal-insulator-metal (MIM) structure that includes a semiconducting monolayer crystalline non-metallic atomic sheet sandwiched between a top metal electrode and a bottom metal electrode. The 2DNS is able to perform stable non-volatile resistance switching, including both unipolar and bipolar switching, with a high ON/OFF ratio, low ON resistance, and low operating voltage. The monolayer atomic sheet may include hexagonal boron nitride (h-BN) or a transition metal dichalcogenide (TMD), such as MoS2, MoSe2, WS2, or WSe2. The present disclosure also provides methods for synthesizing a semiconducting monolayer crystalline non-metallic atomic sheet on a target substrate. The monolayer atomic sheet may include h-BN or a TMD, such as MoS2, MoSe2, WS2, or WSe2.Type: ApplicationFiled: May 25, 2021Publication date: December 30, 2021Inventors: DEJI AKINWANDE, XIAOHAN WU, RUIJING GE, JACK C. LEE
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Patent number: 10312355Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.Type: GrantFiled: December 6, 2017Date of Patent: June 4, 2019Assignee: The Board of Regents of the University of Texas SystemInventors: Jack C. Lee, Han Zhao
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Publication number: 20180108761Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.Type: ApplicationFiled: December 6, 2017Publication date: April 19, 2018Applicant: The Board of Regents of The University of Texas SystemInventors: JACK C. LEE, Han Zhao
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Patent number: 9853135Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.Type: GrantFiled: January 26, 2016Date of Patent: December 26, 2017Assignee: THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEMInventors: Jack C. Lee, Han Zhao
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Publication number: 20160163840Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.Type: ApplicationFiled: January 26, 2016Publication date: June 9, 2016Applicant: THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEMInventors: JACK C. LEE, HAN ZHAO
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Patent number: 9293591Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.Type: GrantFiled: October 14, 2011Date of Patent: March 22, 2016Assignee: THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEMInventors: Jack C. Lee, Han Zhao
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Publication number: 20150364572Abstract: A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.Type: ApplicationFiled: August 27, 2015Publication date: December 17, 2015Inventors: Jack C. Lee, Fei Xue
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Patent number: 9209271Abstract: A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.Type: GrantFiled: August 27, 2015Date of Patent: December 8, 2015Assignee: Board of Regents, The University of Texas SystemInventors: Jack C. Lee, Fei Xue
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Patent number: 9048330Abstract: A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with a gate wrapped around these one or more channel layers. Additionally, the GWAFET includes a barrier layer residing on the top channel layer with a layer of doped III-V semiconductor material residing on each end of the barrier layer. A source and drain contact are connected to the layer of doped III-V semiconductor material as well as to the multiple channels in the embodiment with the GWAFET including multiple channel layers. By having such a structure, integration density is improved. Furthermore, electrostatic control is improved due to gate coupling, which helps reduce standby power consumption. Furthermore, by using III-V semiconductor material as opposed to silicon, the current drive capacity is improved.Type: GrantFiled: August 28, 2013Date of Patent: June 2, 2015Assignee: Board of Regents, The University of Texas SystemInventors: Jack C. Lee, Fei Xue
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Publication number: 20150060957Abstract: A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with a gate wrapped around these one or more channel layers. Additionally, the GWAFET includes a barrier layer residing on the top channel layer with a layer of doped III-V semiconductor material residing on each end of the barrier layer. A source and drain contact are connected to the layer of doped III-V semiconductor material as well as to the multiple channels in the embodiment with the GWAFET including multiple channel layers. By having such a structure, integration density is improved. Furthermore, electrostatic control is improved due to gate coupling, which helps reduce standby power consumption. Furthermore, by using III-V semiconductor material as opposed to silicon, the current drive capacity is improved.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Applicant: Board of Regents, The University of Texas SystemInventors: Jack C. Lee, Fei Xue
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Publication number: 20150053929Abstract: A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.Type: ApplicationFiled: August 22, 2013Publication date: February 26, 2015Applicant: Board of Regents. The University of Texas SystemInventors: Jack C. Lee, Fei Xue
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Publication number: 20130093497Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Applicant: The Board of Regents of The University of Texas SystemInventors: Jack C. Lee, Han Zhao
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Patent number: 6243502Abstract: A method and system is presented for improving and/or maintaining the quality of a digital image file by preserving information that was included at image capture and lost during an image editing/processing operation. Generally, image-description information is stored in structured fields that collectively are described as the image's header. The image's header are stored in an image's file in addition to the image's pixel values. This invention produces and maintains a level of quality of the original enriched image files. This is accomplished by extracting image-description information prior to the processing of an image by an editing package, by selecting, storing and preserving the image-descriptive information data. The so stored data is combined with the editing package's processed image file, to produce an enriched processed image file. The enriched files includes the preserved data which would otherwise be discards.Type: GrantFiled: August 13, 1998Date of Patent: June 5, 2001Assignee: International Business Machines CorporationInventors: James Christensen, Jack C. Lee
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Patent number: 6146934Abstract: A PMOS or CMOS device includes an active region with a shallow heavy atom p-type implant. The PMOS device has a substrate, at least one gate electrode disposed on the substrate, and first and second doped active regions disposed adjacent to the gate electrode. The first active region has a higher concentration of a p-type heavy atom dopant material than the second active region. In one method of forming the PMOS device, spacers are formed on sidewalls of the gate electrode. A first p-type dopant material is selectively implanted into active regions adjacent to the gate electrode using the spacers as a mask. Then a portion of one of the spacers is removed to form a thinner spacer and a second p-type dopant material is selectively implanted into a first one of the active regions using the thinner spacer as a mask. The second p-type dopant material is a heavy atom species.Type: GrantFiled: December 19, 1997Date of Patent: November 14, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, H. Jim Fulford, Jack C. Lee
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Patent number: 6057584Abstract: A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.Type: GrantFiled: December 19, 1997Date of Patent: May 2, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Mark C. Gilmer, H. Jim Fulford, Jack C. Lee
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Patent number: 6013546Abstract: A semiconductor device is formed which includes a shallow PMOS active region containing a heavy atom p-type dopant material. In an exemplary process for making a PMOS device or portion of a device, at least one PMOS gate electrode is formed over a PMOS device region of a substrate. A PMOS spacer is formed on a sidewall of a PMOS gate electrode. An amorphizing dopant material is selectively implanted into a PMOS active region using the PMOS spacer as a mask. A heavy atom p-type dopant material is selectively implanted into the PMOS active region using the PMOS spacer as a mask. The order of implantation of the amorphizing dopant material and the heavy atom p-type dopant material may be reversed.Type: GrantFiled: December 19, 1997Date of Patent: January 11, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, H. Jim Fulford, Jack C. Lee
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Patent number: 5029107Abstract: Apparatus and an accompanying method for converting a relatively high resolution halftone bit-mapped monochromatic document, such as illustratively a halftone separation which exists in a CDPF print file, into a relatively low resolution continuous tone grey scale document which, when the latter is applied to a display screen of a video monitor having appropriate grey scale capability, would provide a readable displayed page, i.e. a "preview", that approximately depicts how the bit-mapped document would appear when printed.Type: GrantFiled: March 31, 1989Date of Patent: July 2, 1991Assignee: International Business CorporationInventor: Jack C. Lee